arch, cpu: Remove float type accessors.

[gem5.git] / src / cpu / o3 / thread_context_impl.hh

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
old mode 100755 (executable)
new mode 100644 (file)
index d9f84fb..f4b5cb4
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -199,18 +199,11 @@ O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
     return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
-template <class Impl>
-TheISA::FloatReg
-O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
-{
-    return cpu->readArchFloatReg(reg_idx, thread->threadId());
-}
-
 template <class Impl>
 TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
 {
-    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
+    return cpu->readArchFloatRegBits(reg_idx, thread->threadId());
 }
 
 template <class Impl>
@@ -251,20 +244,11 @@ O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
     conditionalSquash();
 }
 
-template <class Impl>
-void
-O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
-{
-    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
-
-    conditionalSquash();
-}
-
 template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
 {
-    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
+    cpu->setArchFloatRegBits(reg_idx, val, thread->threadId());
 
     conditionalSquash();
 }