CPU: Tidy up endianness handling for mmapped "IPR"s.

[gem5.git] / src / cpu / ozone / OzoneCPU.py

diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index 37386898d1682c78636630197b2bf5c7cda964c9..2c7b8475fd785c52ef0b3f418f7c44bb21b6773f 100644 (file)
--- a/src/cpu/ozone/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -26,11 +26,11 @@
 #
 # Authors: Kevin Lim
 
+from m5.defines import buildEnv
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
-if build_env['USE_CHECKER']:
+if buildEnv['USE_CHECKER']:
     from OzoneChecker import OzoneChecker
 
 class DerivOzoneCPU(BaseCPU):
@@ -38,7 +38,7 @@ class DerivOzoneCPU(BaseCPU):
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if build_env['USE_CHECKER']:
+    if buildEnv['USE_CHECKER']:
         checker = Param.BaseCPU("Checker CPU")
 
     icache_port = Port("Instruction Port")