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O3: When squashing, restore the macroop that should be used for fetching.
[gem5.git] / src / cpu / ozone / back_end.hh
diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh
index 84429f3c1b10ebfe4d0d5cb5f6b4923ad8951166..90a336d1b0001d02639eecedfe889a9f59f867f5 100644 (file)
--- a/src/cpu/ozone/back_end.hh
+++ b/src/cpu/ozone/back_end.hh
@@ -35,13 +35,13 @@
 #include <queue>
 #include <string>
 
-#include "sim/faults.hh"
-#include "base/timebuf.hh"
-#include "cpu/inst_seq.hh"
 #include "cpu/ozone/rename_table.hh"
 #include "cpu/ozone/thread_state.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/timebuf.hh"
 #include "mem/request.hh"
 #include "sim/eventq.hh"
+#include "sim/faults.hh"
 
 class ThreadContext;
 
@@ -157,13 +157,13 @@ class BackEnd
         int numInsts;
         int width;
 
-        Stats::VectorDistribution<> occ_dist;
+        Stats::VectorDistribution occ_dist;
 
-        Stats::Vector<> inst_count;
-        Stats::Vector<> peak_inst_count;
-        Stats::Scalar<> empty_count;
-        Stats::Scalar<> current_count;
-        Stats::Scalar<> fullCount;
+        Stats::Vector inst_count;
+        Stats::Vector peak_inst_count;
+        Stats::Scalar empty_count;
+        Stats::Scalar current_count;
+        Stats::Scalar fullCount;
 
         Stats::Formula occ_rate;
         Stats::Formula avg_residency;
@@ -371,45 +371,45 @@ class BackEnd
     bool fetchRedirect[Impl::MaxThreads];
 
     // number of cycles stalled for D-cache misses
-/*    Stats::Scalar<> dcacheStallCycles;
+/*    Stats::Scalar dcacheStallCycles;
       Counter lastDcacheStall;
 */
-    Stats::Vector<> rob_cap_events;
-    Stats::Vector<> rob_cap_inst_count;
-    Stats::Vector<> iq_cap_events;
-    Stats::Vector<> iq_cap_inst_count;
+    Stats::Vector rob_cap_events;
+    Stats::Vector rob_cap_inst_count;
+    Stats::Vector iq_cap_events;
+    Stats::Vector iq_cap_inst_count;
     // total number of instructions executed
-    Stats::Vector<> exe_inst;
-    Stats::Vector<> exe_swp;
-    Stats::Vector<> exe_nop;
-    Stats::Vector<> exe_refs;
-    Stats::Vector<> exe_loads;
-    Stats::Vector<> exe_branches;
+    Stats::Vector exe_inst;
+    Stats::Vector exe_swp;
+    Stats::Vector exe_nop;
+    Stats::Vector exe_refs;
+    Stats::Vector exe_loads;
+    Stats::Vector exe_branches;
 
-    Stats::Vector<> issued_ops;
+    Stats::Vector issued_ops;
 
     // total number of loads forwaded from LSQ stores
-    Stats::Vector<> lsq_forw_loads;
+    Stats::Vector lsq_forw_loads;
 
     // total number of loads ignored due to invalid addresses
-    Stats::Vector<> inv_addr_loads;
+    Stats::Vector inv_addr_loads;
 
     // total number of software prefetches ignored due to invalid addresses
-    Stats::Vector<> inv_addr_swpfs;
+    Stats::Vector inv_addr_swpfs;
     // ready loads blocked due to memory disambiguation
-    Stats::Vector<> lsq_blocked_loads;
+    Stats::Vector lsq_blocked_loads;
 
-    Stats::Scalar<> lsqInversion;
+    Stats::Scalar lsqInversion;
 
-    Stats::Vector<> n_issued_dist;
-    Stats::VectorDistribution<> issue_delay_dist;
+    Stats::Vector n_issued_dist;
+    Stats::VectorDistribution issue_delay_dist;
 
-    Stats::VectorDistribution<> queue_res_dist;
+    Stats::VectorDistribution queue_res_dist;
 /*
-    Stats::Vector<> stat_fu_busy;
-    Stats::Vector2d<> stat_fuBusy;
-    Stats::Vector<> dist_unissued;
-    Stats::Vector2d<> stat_issued_inst_type;
+    Stats::Vector stat_fu_busy;
+    Stats::Vector2d stat_fuBusy;
+    Stats::Vector dist_unissued;
+    Stats::Vector2d stat_issued_inst_type;
 
     Stats::Formula misspec_cnt;
     Stats::Formula misspec_ipc;
@@ -422,34 +422,34 @@ class BackEnd
     Stats::Formula commit_ipb;
     Stats::Formula lsq_inv_rate;
 */
-    Stats::Vector<> writeback_count;
-    Stats::Vector<> producer_inst;
-    Stats::Vector<> consumer_inst;
-    Stats::Vector<> wb_penalized;
+    Stats::Vector writeback_count;
+    Stats::Vector producer_inst;
+    Stats::Vector consumer_inst;
+    Stats::Vector wb_penalized;
 
     Stats::Formula wb_rate;
     Stats::Formula wb_fanout;
     Stats::Formula wb_penalized_rate;
 
     // total number of instructions committed
-    Stats::Vector<> stat_com_inst;
-    Stats::Vector<> stat_com_swp;
-    Stats::Vector<> stat_com_refs;
-    Stats::Vector<> stat_com_loads;
-    Stats::Vector<> stat_com_membars;
-    Stats::Vector<> stat_com_branches;
+    Stats::Vector stat_com_inst;
+    Stats::Vector stat_com_swp;
+    Stats::Vector stat_com_refs;
+    Stats::Vector stat_com_loads;
+    Stats::Vector stat_com_membars;
+    Stats::Vector stat_com_branches;
 
-    Stats::Distribution<> n_committed_dist;
+    Stats::Distribution n_committed_dist;
 
-    Stats::Scalar<> commit_eligible_samples;
-    Stats::Vector<> commit_eligible;
+    Stats::Scalar commit_eligible_samples;
+    Stats::Vector commit_eligible;
 
-    Stats::Scalar<> ROB_fcount;
+    Stats::Scalar ROB_fcount;
     Stats::Formula ROB_full_rate;
 
-    Stats::Vector<>  ROB_count;  // cumulative ROB occupancy
+    Stats::Vector  ROB_count;  // cumulative ROB occupancy
     Stats::Formula ROB_occ_rate;
-    Stats::VectorDistribution<> ROB_occ_dist;
+    Stats::VectorDistribution ROB_occ_dist;
   public:
     void dumpInsts();
 };
@@ -468,7 +468,7 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
     if (fault == NoFault && dcacheInterface) {
         memReq->cmd = Read;
         memReq->completionEvent = NULL;
-        memReq->time = curTick;
+        memReq->time = curTick();
         memReq->flags &= ~INST_READ;
         MemAccessResult result = dcacheInterface->access(memReq);
 
@@ -481,7 +481,7 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
             --funcExeInst;
 
             memReq->completionEvent = &cacheCompletionEvent;
-            lastDcacheStall = curTick;
+            lastDcacheStall = curTick();
 //          unscheduleTickEvent();
 //          status = DcacheMissStall;
             DPRINTF(OzoneCPU, "Dcache miss stall!\n");
@@ -491,10 +491,6 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
 
         }
     }
-*/
-/*
-    if (!dcacheInterface && (memReq->isUncacheable()))
-        recordEvent("Uncached Read");
 */
     return LSQ.read(req, data, load_idx);
 }
@@ -514,7 +510,7 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
         memReq->cmd = Write;
         memcpy(memReq->data,(uint8_t *)&data,memReq->size);
         memReq->completionEvent = NULL;
-        memReq->time = curTick;
+        memReq->time = curTick();
         memReq->flags &= ~INST_READ;
         MemAccessResult result = dcacheInterface->access(memReq);
 
@@ -523,7 +519,7 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
         // at some point.
         if (result != MA_HIT && dcacheInterface->doEvents()) {
             memReq->completionEvent = &cacheCompletionEvent;
-            lastDcacheStall = curTick;
+            lastDcacheStall = curTick();
 //          unscheduleTickEvent();
 //          status = DcacheMissStall;
             DPRINTF(OzoneCPU, "Dcache miss stall!\n");
@@ -533,10 +529,6 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
     if (res && (fault == NoFault))
         *res = memReq->result;
         */
-/*
-    if (!dcacheInterface && (memReq->isUncacheable()))
-        recordEvent("Uncached Write");
-*/
     return LSQ.write(req, data, store_idx);
 }