+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
#ifndef __CPU_OZONE_BACK_END_HH__
#define __CPU_OZONE_BACK_END_HH__
#include <queue>
#include <string>
-#include "arch/faults.hh"
+#include "sim/faults.hh"
#include "base/timebuf.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ozone/rename_table.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
-class ExecContext;
+class ThreadContext;
template <class Impl>
class OzoneThreadState;
int numInsts;
int width;
- Stats::VectorDistribution<> occ_dist;
+ Stats::VectorDistribution occ_dist;
- Stats::Vector<> inst_count;
- Stats::Vector<> peak_inst_count;
- Stats::Scalar<> empty_count;
- Stats::Scalar<> current_count;
- Stats::Scalar<> fullCount;
+ Stats::Vector inst_count;
+ Stats::Vector peak_inst_count;
+ Stats::Scalar empty_count;
+ Stats::Scalar current_count;
+ Stats::Scalar fullCount;
Stats::Formula occ_rate;
Stats::Formula avg_residency;
/** Processes writeback event. */
virtual void process();
/** Returns the description of the writeback event. */
- virtual const char *description();
+ virtual const char *description() const;
};
BackEnd(Params *params);
void setFrontEnd(FrontEnd *front_end_ptr)
{ frontEnd = front_end_ptr; }
- void setXC(ExecContext *xc_ptr)
- { xc = xc_ptr; }
+ void setTC(ThreadContext *tc_ptr)
+ { tc = tc_ptr; }
void setThreadState(Thread *thread_ptr)
{ thread = thread_ptr; }
void tick();
void squash();
- void squashFromXC();
- bool xcSquash;
+ void squashFromTC();
+ bool tcSquash;
template <class T>
Fault read(RequestPtr req, T &data, int load_idx);
FrontEnd *frontEnd;
- ExecContext *xc;
+ ThreadContext *tc;
Thread *thread;
DCacheCompletionEvent(BackEnd *_be);
virtual void process();
- virtual const char *description();
+ virtual const char *description() const;
};
friend class DCacheCompletionEvent;
bool fetchRedirect[Impl::MaxThreads];
// number of cycles stalled for D-cache misses
-/* Stats::Scalar<> dcacheStallCycles;
+/* Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
*/
- Stats::Vector<> rob_cap_events;
- Stats::Vector<> rob_cap_inst_count;
- Stats::Vector<> iq_cap_events;
- Stats::Vector<> iq_cap_inst_count;
+ Stats::Vector rob_cap_events;
+ Stats::Vector rob_cap_inst_count;
+ Stats::Vector iq_cap_events;
+ Stats::Vector iq_cap_inst_count;
// total number of instructions executed
- Stats::Vector<> exe_inst;
- Stats::Vector<> exe_swp;
- Stats::Vector<> exe_nop;
- Stats::Vector<> exe_refs;
- Stats::Vector<> exe_loads;
- Stats::Vector<> exe_branches;
+ Stats::Vector exe_inst;
+ Stats::Vector exe_swp;
+ Stats::Vector exe_nop;
+ Stats::Vector exe_refs;
+ Stats::Vector exe_loads;
+ Stats::Vector exe_branches;
- Stats::Vector<> issued_ops;
+ Stats::Vector issued_ops;
// total number of loads forwaded from LSQ stores
- Stats::Vector<> lsq_forw_loads;
+ Stats::Vector lsq_forw_loads;
// total number of loads ignored due to invalid addresses
- Stats::Vector<> inv_addr_loads;
+ Stats::Vector inv_addr_loads;
// total number of software prefetches ignored due to invalid addresses
- Stats::Vector<> inv_addr_swpfs;
+ Stats::Vector inv_addr_swpfs;
// ready loads blocked due to memory disambiguation
- Stats::Vector<> lsq_blocked_loads;
+ Stats::Vector lsq_blocked_loads;
- Stats::Scalar<> lsqInversion;
+ Stats::Scalar lsqInversion;
- Stats::Vector<> n_issued_dist;
- Stats::VectorDistribution<> issue_delay_dist;
+ Stats::Vector n_issued_dist;
+ Stats::VectorDistribution issue_delay_dist;
- Stats::VectorDistribution<> queue_res_dist;
+ Stats::VectorDistribution queue_res_dist;
/*
- Stats::Vector<> stat_fu_busy;
- Stats::Vector2d<> stat_fuBusy;
- Stats::Vector<> dist_unissued;
- Stats::Vector2d<> stat_issued_inst_type;
+ Stats::Vector stat_fu_busy;
+ Stats::Vector2d stat_fuBusy;
+ Stats::Vector dist_unissued;
+ Stats::Vector2d stat_issued_inst_type;
Stats::Formula misspec_cnt;
Stats::Formula misspec_ipc;
Stats::Formula commit_ipb;
Stats::Formula lsq_inv_rate;
*/
- Stats::Vector<> writeback_count;
- Stats::Vector<> producer_inst;
- Stats::Vector<> consumer_inst;
- Stats::Vector<> wb_penalized;
+ Stats::Vector writeback_count;
+ Stats::Vector producer_inst;
+ Stats::Vector consumer_inst;
+ Stats::Vector wb_penalized;
Stats::Formula wb_rate;
Stats::Formula wb_fanout;
Stats::Formula wb_penalized_rate;
// total number of instructions committed
- Stats::Vector<> stat_com_inst;
- Stats::Vector<> stat_com_swp;
- Stats::Vector<> stat_com_refs;
- Stats::Vector<> stat_com_loads;
- Stats::Vector<> stat_com_membars;
- Stats::Vector<> stat_com_branches;
+ Stats::Vector stat_com_inst;
+ Stats::Vector stat_com_swp;
+ Stats::Vector stat_com_refs;
+ Stats::Vector stat_com_loads;
+ Stats::Vector stat_com_membars;
+ Stats::Vector stat_com_branches;
- Stats::Distribution<> n_committed_dist;
+ Stats::Distribution n_committed_dist;
- Stats::Scalar<> commit_eligible_samples;
- Stats::Vector<> commit_eligible;
+ Stats::Scalar commit_eligible_samples;
+ Stats::Vector commit_eligible;
- Stats::Scalar<> ROB_fcount;
+ Stats::Scalar ROB_fcount;
Stats::Formula ROB_full_rate;
- Stats::Vector<> ROB_count; // cumulative ROB occupancy
+ Stats::Vector ROB_count; // cumulative ROB occupancy
Stats::Formula ROB_occ_rate;
- Stats::VectorDistribution<> ROB_occ_dist;
+ Stats::VectorDistribution ROB_occ_dist;
public:
void dumpInsts();
};
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
-// status = DcacheMissStall;
+// unscheduleTickEvent();
+// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
} else {
// do functional access
}
}
-*/
-/*
- if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
- recordEvent("Uncached Read");
*/
return LSQ.read(req, data, load_idx);
}
if (result != MA_HIT && dcacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
-// status = DcacheMissStall;
+// unscheduleTickEvent();
+// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
}
}
if (res && (fault == NoFault))
*res = memReq->result;
*/
-/*
- if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
- recordEvent("Uncached Write");
-*/
return LSQ.write(req, data, store_idx);
}