+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
#include "encumbered/cpu/full/op_class.hh"
#include "cpu/ozone/back_end.hh"
template<class Impl>
const char *
-BackEnd<Impl>::LdWritebackEvent::description()
+BackEnd<Impl>::LdWritebackEvent::description() const
{
- return "Load writeback event";
+ return "Load writeback";
}
template <class Impl>
const char *
-BackEnd<Impl>::DCacheCompletionEvent::description()
+BackEnd<Impl>::DCacheCompletionEvent::description() const
{
- return "Cache completion event";
+ return "Cache completion";
}
template <class Impl>
{
using namespace Stats;
rob_cap_events
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ROB:cap_events")
.desc("number of cycles where ROB cap was active")
.flags(total)
;
rob_cap_inst_count
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ROB:cap_inst")
.desc("number of instructions held up by ROB cap")
.flags(total)
;
iq_cap_events
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() +".IQ:cap_events" )
.desc("number of cycles where IQ cap was active")
.flags(total)
;
iq_cap_inst_count
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".IQ:cap_inst")
.desc("number of instructions held up by IQ cap")
.flags(total)
exe_inst
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:count")
.desc("number of insts issued")
.flags(total)
;
exe_swp
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:swp")
.desc("number of swp insts issued")
.flags(total)
;
exe_nop
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:nop")
.desc("number of nop insts issued")
.flags(total)
;
exe_refs
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:refs")
.desc("number of memory reference insts issued")
.flags(total)
;
exe_loads
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:loads")
.desc("number of load insts issued")
.flags(total)
;
exe_branches
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:branches")
.desc("Number of branches issued")
.flags(total)
;
issued_ops
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:op_count")
.desc("number of insts issued")
.flags(total)
// Other stats
//
lsq_forw_loads
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".LSQ:forw_loads")
.desc("number of loads forwarded via LSQ")
.flags(total)
;
inv_addr_loads
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:addr_loads")
.desc("number of invalid-address loads")
.flags(total)
;
inv_addr_swpfs
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ISSUE:addr_swpfs")
.desc("number of invalid-address SW prefetches")
.flags(total)
;
lsq_blocked_loads
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".LSQ:blocked_loads")
.desc("number of ready loads not issued due to memory disambiguation")
.flags(total)
}
writeback_count
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".WB:count")
.desc("cumulative count of insts written-back")
.flags(total)
;
producer_inst
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".WB:producers")
.desc("num instructions producing a value")
.flags(total)
;
consumer_inst
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".WB:consumers")
.desc("num instructions consuming a value")
.flags(total)
;
wb_penalized
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".WB:penalized")
.desc("number of instrctions required to write to 'other' IQ")
.flags(total)
wb_rate = writeback_count / cpu->numCycles;
stat_com_inst
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".COM:count")
.desc("Number of instructions committed")
.flags(total)
;
stat_com_swp
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".COM:swp_count")
.desc("Number of s/w prefetches committed")
.flags(total)
;
stat_com_refs
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".COM:refs")
.desc("Number of memory references committed")
.flags(total)
;
stat_com_loads
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".COM:loads")
.desc("Number of loads committed")
.flags(total)
;
stat_com_membars
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".COM:membars")
.desc("Number of memory barriers committed")
.flags(total)
;
stat_com_branches
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".COM:branches")
.desc("Number of branches committed")
.flags(total)
// we reached the BW limit
//
commit_eligible
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".COM:bw_limited")
.desc("number of insts not committed due to BW limits")
.flags(total)
;
ROB_count
- .init(cpu->number_of_threads)
+ .init(cpu->numThreads)
.name(name() + ".ROB:occupancy")
.desc(name() + ".ROB occupancy (cumulative)")
.flags(total)
ROB_occ_rate = ROB_count / cpu->numCycles;
ROB_occ_dist
- .init(cpu->number_of_threads,0,numROBEntries,2)
+ .init(cpu->numThreads, 0, numROBEntries, 2)
.name(name() + ".ROB:occ_dist")
.desc("ROB Occupancy per cycle")
.flags(total | cdf)
// ++iewExecStoreInsts;
- if (!(inst->req->flags & LOCKED)) {
+ if (!(inst->req->isLLSC())) {
inst->setExecuted();
instToCommit(inst);
// This probably needs to prioritize the redirects if a different
// scheduler is used. Currently the scheduler schedules the oldest
// instruction first, so the branch resolution order will be correct.
- unsigned tid = inst->threadNumber;
+ ThreadID tid = inst->threadNumber;
if (!fetchRedirect[tid]) {
void
BackEnd<Impl>::updateExeInstStats(DynInstPtr &inst)
{
- int thread_number = inst->threadNumber;
+ ThreadID tid = inst->threadNumber;
//
// Pick off the software prefetches
//
#ifdef TARGET_ALPHA
if (inst->isDataPrefetch())
- exe_swp[thread_number]++;
+ exe_swp[tid]++;
else
- exe_inst[thread_number]++;
+ exe_inst[tid]++;
#else
- exe_inst[thread_number]++;
+ exe_inst[tid]++;
#endif
//
// Control operations
//
if (inst->isControl())
- exe_branches[thread_number]++;
+ exe_branches[tid]++;
//
// Memory operations
//
if (inst->isMemRef()) {
- exe_refs[thread_number]++;
+ exe_refs[tid]++;
if (inst->isLoad())
- exe_loads[thread_number]++;
+ exe_loads[tid]++;
}
}
void
BackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
{
- unsigned thread = inst->threadNumber;
+ ThreadID tid = inst->threadNumber;
//
// Pick off the software prefetches
//
#ifdef TARGET_ALPHA
if (inst->isDataPrefetch()) {
- stat_com_swp[thread]++;
+ stat_com_swp[tid]++;
} else {
- stat_com_inst[thread]++;
+ stat_com_inst[tid]++;
}
#else
- stat_com_inst[thread]++;
+ stat_com_inst[tid]++;
#endif
//
// Control Instructions
//
if (inst->isControl())
- stat_com_branches[thread]++;
+ stat_com_branches[tid]++;
//
// Memory references
//
if (inst->isMemRef()) {
- stat_com_refs[thread]++;
+ stat_com_refs[tid]++;
if (inst->isLoad()) {
- stat_com_loads[thread]++;
+ stat_com_loads[tid]++;
}
}
if (inst->isMemBarrier()) {
- stat_com_membars[thread]++;
+ stat_com_membars[tid]++;
}
}
projects / gem5.git / blobdiff