MEM: Introduce the master/slave port sub-classes in C++

[gem5.git] / src / cpu / ozone / cpu_impl.hh

diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index b111d4425640c70751704766e27ce5a41bc268d0..3a32c07c65006543162068873c57e3a8da26cd73 100644 (file)
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -390,18 +390,6 @@ OzoneCPU<Impl>::init()
     thread.inSyscall = false;
 }
 
-template <class Impl>
-Port *
-OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
-{
-    if (if_name == "dcache_port")
-        return backEnd->getDcachePort();
-    else if (if_name == "icache_port")
-        return frontEnd->getIcachePort();
-    else
-        panic("No Such Port\n");
-}
-
 template <class Impl>
 void
 OzoneCPU<Impl>::serialize(std::ostream &os)