#include "arch/isa_traits.hh"
#include "arch/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ozone/cpu.hh" // MUST include this
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readIntResult();
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
- {
- switch(width) {
- case 32:
- return srcInsts[idx]->readFloatResult();
- case 64:
- return srcInsts[idx]->readDoubleResult();
- default:
- panic("Width not supported");
- return 0;
- }
- }
-
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readFloatResult();
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
- return srcInsts[idx]->readIntResult();
+ return srcInsts[idx]->readFloatResult();
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return srcInsts[idx]->readIntResult();
}
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
BaseDynInst<Impl>::setIntReg(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
- {
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
- }
-
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
BaseDynInst<Impl>::setFloatReg(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
- {
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
- }
-
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
public:
// ISA stuff
+ MiscReg readMiscRegNoEffect(int misc_reg);
+
MiscReg readMiscReg(int misc_reg);
- MiscReg readMiscRegWithEffect(int misc_reg);
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val);
- void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
-
#if FULL_SYSTEM
Fault hwrei();
- bool inPalMode();
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else