CPU: Get rid of the now unnecessary getInst/setInst family of functions.

[gem5.git] / src / cpu / ozone / dyn_inst.hh

diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 7c1e17074f4b2dfa6c0c84f54c91dddd8106218c..cca72ef18fcc4023b18a023e5cd8391b535543a3 100644 (file)
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -24,17 +24,20 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
  */
 
 #ifndef __CPU_OZONE_DYN_INST_HH__
 #define __CPU_OZONE_DYN_INST_HH__
 
 #include "arch/isa_traits.hh"
+#include "arch/types.hh"
 #include "config/full_system.hh"
+#include "config/the_isa.hh"
 #include "cpu/base_dyn_inst.hh"
-#include "cpu/ozone/cpu.hh"   // MUST include this
 #include "cpu/inst_seq.hh"
-//#include "cpu/ozone/simple_impl.hh" // Would be nice to not have to include this
+#include "cpu/ozone/cpu.hh"   // MUST include this
 #include "cpu/ozone/ozone_impl.hh"
 
 #include <list>
@@ -45,15 +48,17 @@ class OzoneDynInst : public BaseDynInst<Impl>
 {
   public:
     // Typedefs
-    typedef typename Impl::FullCPU FullCPU;
+    typedef typename Impl::OzoneCPU OzoneCPU;
 
-    typedef typename FullCPU::ImplState ImplState;
+    typedef typename OzoneCPU::ImplState ImplState;
 
     // Typedef for DynInstPtr.  This is really just a RefCountingPtr<OoODynInst>.
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     typedef TheISA::ExtMachInst ExtMachInst;
     typedef TheISA::MachInst MachInst;
+    typedef TheISA::FloatReg FloatReg;
+    typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::MiscReg MiscReg;
     typedef typename std::list<DynInstPtr>::iterator ListIt;
 
@@ -65,10 +70,10 @@ class OzoneDynInst : public BaseDynInst<Impl>
         MaxInstDestRegs = TheISA::MaxInstDestRegs
     };
 
-    OzoneDynInst(FullCPU *cpu);
+    OzoneDynInst(OzoneCPU *cpu);
 
     OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
-                 InstSeqNum seq_num, FullCPU *cpu);
+                 InstSeqNum seq_num, OzoneCPU *cpu);
 
     OzoneDynInst(StaticInstPtr inst);
 
@@ -129,7 +134,7 @@ class OzoneDynInst : public BaseDynInst<Impl>
 
     Fault initiateAcc();
 
-    Fault completeAcc();
+    Fault completeAcc(PacketPtr pkt);
 
     // The register accessor methods provide the index of the
     // instruction's operand (e.g., 0 or 1), not the architectural
@@ -142,22 +147,22 @@ class OzoneDynInst : public BaseDynInst<Impl>
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst *si, int idx)
+    uint64_t readIntRegOperand(const StaticInst *si, int idx)
     {
         return srcInsts[idx]->readIntResult();
     }
 
-    float readFloatRegSingle(const StaticInst *si, int idx)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         return srcInsts[idx]->readFloatResult();
     }
 
-    double readFloatRegDouble(const StaticInst *si, int idx)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
-        return srcInsts[idx]->readDoubleResult();
+        return srcInsts[idx]->readFloatResult();
     }
 
-    uint64_t readFloatRegInt(const StaticInst *si, int idx)
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         return srcInsts[idx]->readIntResult();
     }
@@ -165,24 +170,20 @@ class OzoneDynInst : public BaseDynInst<Impl>
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
-    void setIntReg(const StaticInst *si, int idx, uint64_t val)
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
     {
         BaseDynInst<Impl>::setIntReg(si, idx, val);
     }
 
-    void setFloatRegSingle(const StaticInst *si, int idx, float val)
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
-        BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
+        BaseDynInst<Impl>::setFloatReg(si, idx, val);
     }
 
-    void setFloatRegDouble(const StaticInst *si, int idx, double val)
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val)
     {
-        BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
-    }
-
-    void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
-    {
-        BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
+        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
     }
 
     void setIntResult(uint64_t result) { this->instResult.integer = result; }
@@ -205,23 +206,20 @@ class OzoneDynInst : public BaseDynInst<Impl>
 
   public:
     // ISA stuff
-    MiscReg readMiscReg(int misc_reg);
+    MiscReg readMiscRegNoEffect(int misc_reg);
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+    MiscReg readMiscReg(int misc_reg);
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val);
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    void setMiscReg(int misc_reg, const MiscReg &val);
 
 #if FULL_SYSTEM
     Fault hwrei();
-    int readIntrFlag();
-    void setIntrFlag(int val);
-    bool inPalMode();
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
 #else
-    void syscall();
+    void syscall(uint64_t &callnum);
 #endif
 
     ListIt iqIt;