#include "arch/isa_traits.hh"
#include "arch/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ozone/cpu.hh" // MUST include this
return srcInsts[idx]->readIntResult();
}
- FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
- {
- switch(width) {
- case 32:
- return srcInsts[idx]->readFloatResult();
- case 64:
- return srcInsts[idx]->readDoubleResult();
- default:
- panic("Width not supported");
- return 0;
- }
- }
-
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readFloatResult();
}
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
- int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
- return srcInsts[idx]->readIntResult();
+ return srcInsts[idx]->readFloatResult();
}
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
BaseDynInst<Impl>::setIntReg(si, idx, val);
}
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
- int width)
- {
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
- }
-
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
BaseDynInst<Impl>::setFloatReg(si, idx, val);
}
- void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
- {
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
- }
-
void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val)
{
void setMiscReg(int misc_reg, const MiscReg &val);
#if FULL_SYSTEM
+ Fault hwrei();
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else