CPU: Get rid of the now unnecessary getInst/setInst family of functions.

[gem5.git] / src / cpu / ozone / inorder_back_end_impl.hh

diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 8aef9c074c4e2d84aa89bc056c30c02327be1349..b48e8f6924e15fee6f66befaf1a244b66b9b57c0 100644 (file)
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -30,6 +30,7 @@
 
 #include "sim/faults.hh"
 #include "arch/types.hh"
+#include "config/the_isa.hh"
 #include "cpu/ozone/inorder_back_end.hh"
 #include "cpu/ozone/thread_state.hh"
 
@@ -88,15 +89,14 @@ InorderBackEnd<Impl>::checkInterrupts()
     int ipl = 0;
     int summary = 0;
 
-    cpu->checkInterrupts = false;
 
-    if (thread->readMiscReg(IPR_ASTRR))
+    if (thread->readMiscRegNoEffect(IPR_ASTRR))
         panic("asynchronous traps not implemented\n");
 
-    if (thread->readMiscReg(IPR_SIRR)) {
+    if (thread->readMiscRegNoEffect(IPR_SIRR)) {
         for (int i = INTLEVEL_SOFTWARE_MIN;
              i < INTLEVEL_SOFTWARE_MAX; i++) {
-            if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+            if (thread->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                 // See table 4-19 of the 21164 hardware reference
                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                 summary |= (ULL(1) << i);
@@ -117,14 +117,14 @@ InorderBackEnd<Impl>::checkInterrupts()
         }
     }
 
-    if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
+    if (ipl && ipl > thread->readMiscRegNoEffect(IPR_IPLR)) {
         thread->inSyscall = true;
 
-        thread->setMiscReg(IPR_ISR, summary);
-        thread->setMiscReg(IPR_INTID, ipl);
+        thread->setMiscRegNoEffect(IPR_ISR, summary);
+        thread->setMiscRegNoEffect(IPR_INTID, ipl);
         Fault(new InterruptFault)->invoke(xc);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                thread->readMiscReg(IPR_IPLR), ipl, summary);
+                thread->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
 
         // May need to go 1 inst prior
         squashPending = true;
@@ -150,13 +150,11 @@ InorderBackEnd<Impl>::tick()
     // if (interrupt) then set thread PC, stall front end, record that
     // I'm waiting for it to drain.  (for now just squash)
 #if FULL_SYSTEM
-    if (interruptBlocked ||
-        (cpu->checkInterrupts &&
-        cpu->check_interrupts() &&
-        !cpu->inPalMode())) {
+    if (interruptBlocked || cpu->checkInterrupts(tc)) {
         if (!robEmpty()) {
             interruptBlocked = true;
-        } else if (robEmpty() && cpu->inPalMode()) {
+        //AlphaDep
+        } else if (robEmpty() && (PC & 0x3)) {
             // Will need to let the front end continue a bit until
             // we're out of pal mode.  Hopefully we never get into an
             // infinite loop...
@@ -306,12 +304,6 @@ InorderBackEnd<Impl>::executeInsts()
 
             thread->inSyscall = true;
 
-            // Hack for now; DTB will sometimes need the machine instruction
-            // for when faults happen.  So we will set it here, prior to the
-            // DTB possibly needing it for this translation.
-            thread->setInst(
-                static_cast<TheISA::MachInst>(inst->staticInst->machInst));
-
             // Consider holding onto the trap and waiting until the trap event
             // happens for this to be executed.
             inst_fault->invoke(xc);
@@ -540,7 +532,7 @@ InorderBackEnd<Impl>::DCacheCompletionEvent::process()
 
 template <class Impl>
 const char *
-InorderBackEnd<Impl>::DCacheCompletionEvent::description()
+InorderBackEnd<Impl>::DCacheCompletionEvent::description() const
 {
-    return "DCache completion event";
+    return "DCache completion";
 }