#ifndef __CPU_OZONE_LW_LSQ_HH__
#define __CPU_OZONE_LW_LSQ_HH__
+#include <algorithm>
#include <list>
#include <map>
#include <queue>
-#include <algorithm>
#include "arch/faults.hh"
#include "arch/types.hh"
-#include "config/full_system.hh"
+#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
+#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
/** Pointer to the back-end stage. */
BackEnd *be;
- MemObject *mem;
-
class DcachePort : public Port
{
protected:
virtual void recvStatusChange(Status status);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
virtual bool recvTiming(PacketPtr pkt);
};
/** Derived class to hold any sender state the LSQ needs. */
- class LSQSenderState : public Packet::SenderState
+ class LSQSenderState : public Packet::SenderState, public FastAlloc
{
public:
/** Default constructor. */
void process();
/** Returns the description of this event. */
- const char *description();
+ const char *description() const;
private:
/** Instruction whose results are being written back. */
//list<InstSeqNum> mshrSeqNums;
/** Tota number of memory ordering violations. */
- Stats::Scalar<> lsqMemOrderViolation;
+ Stats::Scalar lsqMemOrderViolation;
- //Stats::Scalar<> dcacheStallCycles;
+ //Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
// Make these per thread?
// We'll say this has a 1 cycle load-store forwarding latency
// for now.
// @todo: Need to make this a parameter.
- wb->schedule(curTick);
+ wb->schedule(curTick());
// Should keep track of stat for forwarded data
return NoFault;
DPRINTF(OzoneLSQ, "Doing timing access for inst PC %#x\n",
inst->readPC());
- PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt =
+ new Packet(req,
+ (req->isLLSC() ?
+ MemCmd::LoadLockedReq : Packet::ReadReq),
+ Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
return NoFault;
}
- if (req->isLocked()) {
+ if (req->isLLSC()) {
cpu->lockFlag = true;
}
- if (data_pkt->result != Packet::Success) {
- DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache miss!\n");
- DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
- inst->seqNum);
- } else {
- DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache hit!\n");
- DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
- inst->seqNum);
- }
-
return NoFault;
}