void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Handles completing the send of a store to memory. */
- void storePostSend(Packet *pkt, DynInstPtr &inst);
+ void storePostSend(PacketPtr pkt, DynInstPtr &inst);
/** Completes the store at the specified index. */
void completeStore(DynInstPtr &inst);
/** Pointer to the back-end stage. */
BackEnd *be;
- MemObject *mem;
-
class DcachePort : public Port
{
protected:
virtual void recvStatusChange(Status status);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
virtual bool recvTiming(PacketPtr pkt);
// at the head of the LSQ and are ready to commit (at the head of the ROB
// too).
// @todo: Fix uncached accesses.
- if (req->getFlags() & UNCACHEABLE &&
+ if (req->isUncacheable() &&
(inst != loadQueue.back() || !inst->isAtCommit())) {
DPRINTF(OzoneLSQ, "[sn:%lli] Uncached load and not head of "
"commit/LSQ!\n",
DPRINTF(OzoneLSQ, "Doing timing access for inst PC %#x\n",
inst->readPC());
- PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt =
+ new Packet(req,
+ (req->isLocked() ?
+ MemCmd::LoadLockedReq : Packet::ReadReq),
+ Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
return NoFault;
}
- if (req->getFlags() & LOCKED) {
+ if (req->isLocked()) {
cpu->lockFlag = true;
}
- if (data_pkt->result != Packet::Success) {
- DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache miss!\n");
- DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
- inst->seqNum);
- } else {
- DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache hit!\n");
- DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
- inst->seqNum);
- }
-
return NoFault;
}