* Authors: Kevin Lim
*/
-#include "config/use_checker.hh"
-
#include "arch/faults.hh"
#include "base/str.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
#include "cpu/ozone/lw_lsq.hh"
#include "cpu/checker/cpu.hh"
template<class Impl>
const char *
-OzoneLWLSQ<Impl>::WritebackEvent::description()
+OzoneLWLSQ<Impl>::WritebackEvent::description() const
{
return "Store writeback";
}
MemCmd command =
req->isSwap() ? MemCmd::SwapReq :
- (req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
+ (req->isLLSC() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
inst->seqNum);
// @todo: Remove this SC hack once the memory system handles it.
- if (req->isLocked()) {
+ if (req->isLLSC()) {
if (req->isUncacheable()) {
req->setExtraData(2);
} else {
if (result != MA_HIT && dcacheInterface->doEvents()) {
store_event->miss = true;
typename BackEnd::LdWritebackEvent *wb = NULL;
- if (req->isLocked()) {
+ if (req->isLLSC()) {
wb = new typename BackEnd::LdWritebackEvent(inst,
be);
store_event->wbEvent = wb;
// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
// inst->seqNum);
- if (req->isLocked()) {
+ if (req->isLLSC()) {
// Stx_C does not generate a system port
// transaction in the 21264, but that might be
// hard to accomplish in this model.