Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Inter...

[gem5.git] / src / cpu / ozone / ozone_impl.hh

diff --git a/src/cpu/ozone/ozone_impl.hh b/src/cpu/ozone/ozone_impl.hh
index d8c54597764dc944b6b3cd143ca0718905bd5e58..2271cd68ab2fedad748b66c7eedf0a8a2224e408 100644 (file)
--- a/src/cpu/ozone/ozone_impl.hh
+++ b/src/cpu/ozone/ozone_impl.hh
@@ -24,12 +24,13 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
  */
 
 #ifndef __CPU_OZONE_OZONE_IMPL_HH__
 #define __CPU_OZONE_OZONE_IMPL_HH__
 
-#include "arch/alpha/isa_traits.hh"
 #include "cpu/o3/bpred_unit.hh"
 #include "cpu/ozone/front_end.hh"
 #include "cpu/ozone/inst_queue.hh"
@@ -48,11 +49,11 @@ class OzoneDynInst;
 struct OzoneImpl {
     typedef SimpleParams Params;
     typedef OzoneCPU<OzoneImpl> OzoneCPU;
-    typedef OzoneCPU FullCPU;
+    typedef OzoneCPU CPUType;
 
     // Would like to put these into their own area.
 //    typedef NullPredictor BranchPred;
-    typedef TwobitBPredUnit<OzoneImpl> BranchPred;
+    typedef BPredUnit<OzoneImpl> BranchPred;
     typedef FrontEnd<OzoneImpl> FrontEnd;
     // Will need IQ, LSQ eventually
     typedef LWBackEnd<OzoneImpl> BackEnd;