X86: Set up a named constant for the "fold bit" for int register indices.

[gem5.git] / src / cpu / ozone / simple_params.hh

diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index 7b5c6f67bf444865f8f5210a21fffeb71a607b0a..7687fdf60c2b91053e64f547845b70be336e8c65 100644 (file)
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
  */
 
 #ifndef __CPU_OZONE_SIMPLE_PARAMS_HH__
@@ -32,11 +34,12 @@
 #include "cpu/ozone/cpu.hh"
 
 //Forward declarations
-class AlphaDTB;
-class AlphaITB;
+namespace TheISA
+{
+    class TLB;
+}
 class FUPool;
-class FunctionalMemory;
-class MemInterface;
+class MemObject;
 class PageTable;
 class Process;
 class System;
@@ -51,29 +54,27 @@ class SimpleParams : public BaseCPU::Params
 {
   public:
 
-#if FULL_SYSTEM
-    AlphaITB *itb; AlphaDTB *dtb;
-#else
+    TheISA::TLB *itb; TheISA::TLB *dtb;
+#if !FULL_SYSTEM
     std::vector<Process *> workload;
 #endif // FULL_SYSTEM
 
     //Page Table
     PageTable *pTable;
 
-    FunctionalMemory *mem;
-
     //
     // Caches
     //
-    MemInterface *icacheInterface;
-    MemInterface *dcacheInterface;
+//    MemInterface *icacheInterface;
+//    MemInterface *dcacheInterface;
 
     unsigned cachePorts;
     unsigned width;
+    unsigned frontEndLatency;
     unsigned frontEndWidth;
+    unsigned backEndLatency;
     unsigned backEndWidth;
     unsigned backEndSquashLatency;
-    unsigned backEndLatency;
     unsigned maxInstBufferSize;
     unsigned numPhysicalRegs;
     unsigned maxOutstandingMemOps;
@@ -149,6 +150,7 @@ class SimpleParams : public BaseCPU::Params
     //
     unsigned LQEntries;
     unsigned SQEntries;
+    bool lsqLimits;
 
     //
     // Memory dependence