Merge ktlim@zamp:./local/clean/o3-merge/m5

[gem5.git] / src / cpu / ozone / thread_state.hh

diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index e6256e4e367befa1c836909c895c09df07d71c61..adaa8e71bac5c2cb931d7945d217c3674c92d2bc 100644 (file)
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -24,16 +24,22 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
  */
 
 #ifndef __CPU_OZONE_THREAD_STATE_HH__
 #define __CPU_OZONE_THREAD_STATE_HH__
 
 #include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
+#include "arch/regfile.hh"
+#include "base/callback.hh"
+#include "base/output.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
 #include "sim/process.hh"
+#include "sim/sim_exit.hh"
 
 class Event;
 //class Process;
@@ -56,30 +62,36 @@ class FunctionalMemory;
 template <class Impl>
 struct OzoneThreadState : public ThreadState {
     typedef typename ThreadContext::Status Status;
-    typedef typename Impl::FullCPU FullCPU;
+    typedef typename Impl::CPUType CPUType;
     typedef TheISA::MiscReg MiscReg;
 
 #if FULL_SYSTEM
-    OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
-        : ThreadState(-1, _thread_num, _mem),
-          inSyscall(0), trapPending(0)
+    OzoneThreadState(CPUType *_cpu, int _thread_num)
+        : ThreadState(-1, _thread_num),
+          cpu(_cpu), intrflag(0), inSyscall(0), trapPending(0)
     {
-        memset(&regs, 0, sizeof(TheISA::RegFile));
+        if (cpu->params->profile) {
+            profile = new FunctionProfile(cpu->params->system->kernelSymtab);
+            Callback *cb =
+                new MakeCallback<OzoneThreadState,
+                &OzoneThreadState::dumpFuncProfile>(this);
+            registerExitCallback(cb);
+        }
+
+        // let's fill with a dummy node for now so we don't get a segfault
+        // on the first cycle when there's no node available.
+        static ProfileNode dummyNode;
+        profileNode = &dummyNode;
+        profilePC = 3;
+        miscRegFile.clear();
     }
 #else
-    OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
-        : ThreadState(-1, _thread_num, NULL, _process, _asid),
+    OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
+                     int _asid, MemObject *mem)
+        : ThreadState(-1, _thread_num, _process, _asid, mem),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
-        memset(&regs, 0, sizeof(TheISA::RegFile));
-    }
-
-    OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
-                     int _asid)
-        : ThreadState(-1, _thread_num, _mem, NULL, _asid),
-          cpu(_cpu), inSyscall(0), trapPending(0)
-    {
-        memset(&regs, 0, sizeof(TheISA::RegFile));
+        miscRegFile.clear();
     }
 #endif
 
@@ -89,9 +101,11 @@ struct OzoneThreadState : public ThreadState {
 
     Addr nextPC;
 
-    TheISA::RegFile regs;
+    TheISA::MiscRegFile miscRegFile;
+
+    int intrflag;
 
-    typename Impl::FullCPU *cpu;
+    typename Impl::CPUType *cpu;
 
     bool inSyscall;
 
@@ -101,54 +115,24 @@ struct OzoneThreadState : public ThreadState {
 
     ThreadContext *getTC() { return tc; }
 
-#if !FULL_SYSTEM
-    Fault translateInstReq(Request *req)
-    {
-        return process->pTable->translate(req);
-    }
-    Fault translateDataReadReq(Request *req)
-    {
-        return process->pTable->translate(req);
-    }
-    Fault translateDataWriteReq(Request *req)
-    {
-        return process->pTable->translate(req);
-    }
-#else
-    Fault translateInstReq(Request *req)
-    {
-        return cpu->itb->translate(req);
-    }
-
-    Fault translateDataReadReq(Request *req)
-    {
-        return cpu->dtb->translate(req, false);
-    }
-
-    Fault translateDataWriteReq(Request *req)
-    {
-        return cpu->dtb->translate(req, true);
-    }
-#endif
-
     MiscReg readMiscReg(int misc_reg)
     {
-        return regs.readMiscReg(misc_reg);
+        return miscRegFile.readReg(misc_reg);
     }
 
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
     {
-        return regs.readMiscRegWithEffect(misc_reg, fault, tc);
+        return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
     }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscReg(misc_reg, val);
+        return miscRegFile.setReg(misc_reg, val);
     }
 
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscRegWithEffect(misc_reg, val, tc);
+        return miscRegFile.setRegWithEffect(misc_reg, val, tc);
     }
 
     uint64_t readPC()
@@ -162,6 +146,14 @@ struct OzoneThreadState : public ThreadState {
 
     void setNextPC(uint64_t val)
     { nextPC = val; }
+
+#if FULL_SYSTEM
+    void dumpFuncProfile()
+    {
+        std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
+        profile->dump(xcProxy, *os);
+    }
+#endif
 };
 
 #endif // __CPU_OZONE_THREAD_STATE_HH__