cpu: Turn the stage 2 ARM MMUs from params to children.

[gem5.git] / src / cpu / reg_class.cc

diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index 75be4679ddee21ceeb439f994fcf17ac4eb938cf..eeb06adccaf7f373c32d7610d91ecb3ec07bf9d0 100644 (file)
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2016-2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -30,11 +42,13 @@
 
 #include "cpu/reg_class.hh"
 
-const char *RegClassStrings[] = {
+const char *RegId::regClassStrings[] = {
     "IntRegClass",
     "FloatRegClass",
+    "VecRegClass",
+    "VecElemClass",
+    "VecPredRegClass",
     "CCRegClass",
     "MiscRegClass"
 };
 
-const RegId RegId::zeroReg = RegId(IntRegClass, TheISA::ZeroReg);