cpu: Add support for CMOs in the cpu models

[gem5.git] / src / cpu / simple / AtomicSimpleCPU.py

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 1927a586221ff597cc211164b500688c719be8eb..04592c68a001a2d9a18bd4f2969f3446a41e05ce 100644 (file)
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -40,11 +40,30 @@
 
 from m5.params import *
 from BaseSimpleCPU import BaseSimpleCPU
+from SimPoint import SimPoint
 
 class AtomicSimpleCPU(BaseSimpleCPU):
+    """Simple CPU model executing a configurable number of
+    instructions per cycle. This model uses the simplified 'atomic'
+    memory mode."""
+
     type = 'AtomicSimpleCPU'
     cxx_header = "cpu/simple/atomic.hh"
+
+    @classmethod
+    def memory_mode(cls):
+        return 'atomic'
+
+    @classmethod
+    def support_take_over(cls):
+        return True
+
     width = Param.Int(1, "CPU width")
     simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
     fastmem = Param.Bool(False, "Access memory directly")
+
+    def addSimPointProbe(self, interval):
+        simpoint = SimPoint()
+        simpoint.interval = interval
+        self.probeListener = simpoint