sim: Include object header files in SWIG interfaces

[gem5.git] / src / cpu / simple / AtomicSimpleCPU.py

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 54daaec63b795021ff8d75bf8eaec0f8e12daa06..1927a586221ff597cc211164b500688c719be8eb 100644 (file)
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -43,6 +43,7 @@ from BaseSimpleCPU import BaseSimpleCPU
 
 class AtomicSimpleCPU(BaseSimpleCPU):
     type = 'AtomicSimpleCPU'
+    cxx_header = "cpu/simple/atomic.hh"
     width = Param.Int(1, "CPU width")
     simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")