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[gem5.git] / src / cpu / simple / AtomicSimpleCPU.py

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index bfd1825c27ecc91a21cf20689cd4acebc65794fc..a4d807f86460c6b3f507bda967f96b8a7ca246f6 100644 (file)
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -27,18 +27,15 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
-from BaseCPU import BaseCPU
+from BaseSimpleCPU import BaseSimpleCPU
 
-class AtomicSimpleCPU(BaseCPU):
+class AtomicSimpleCPU(BaseSimpleCPU):
     type = 'AtomicSimpleCPU'
     width = Param.Int(1, "CPU width")
-    simulate_stalls = Param.Bool(False, "Simulate cache stall cycles")
-    function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
+    simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
+    simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
-    _mem_ports = ['icache_port', 'dcache_port', 'physmem_port']
+    _cached_ports = BaseSimpleCPU._cached_ports + \
+                    ['icache_port', 'dcache_port']