cpu: Add CPU metadata om the Python classes

[gem5.git] / src / cpu / simple / AtomicSimpleCPU.py

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index b7174bb4396d7cee11404297e3a8fd7283c9c4dc..c747582f624de042349203cb0e1d1554d4dd7883 100644 (file)
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -27,16 +39,25 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseSimpleCPU import BaseSimpleCPU
 
 class AtomicSimpleCPU(BaseSimpleCPU):
+    """Simple CPU model executing a configurable number of
+    instructions per cycle. This model uses the simplified 'atomic'
+    memory mode."""
+
     type = 'AtomicSimpleCPU'
+    cxx_header = "cpu/simple/atomic.hh"
+
+    @classmethod
+    def memory_mode(cls):
+        return 'atomic'
+
+    @classmethod
+    def support_take_over(cls):
+        return True
+
     width = Param.Int(1, "CPU width")
     simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
-    icache_port = Port("Instruction Port")
-    dcache_port = Port("Data Port")
-    physmem_port = Port("Physical Memory Port")
-    _mem_ports = BaseSimpleCPU._mem_ports + \
-                    ['icache_port', 'dcache_port', 'physmem_port']
+    fastmem = Param.Bool(False, "Access memory directly")