need_simple_base = False
if 'AtomicSimpleCPU' in env['CPU_MODELS']:
need_simple_base = True
+ SimObject('AtomicSimpleCPU.py')
Source('atomic.cc')
if 'TimingSimpleCPU' in env['CPU_MODELS']:
need_simple_base = True
+ SimObject('TimingSimpleCPU.py')
Source('timing.cc')
+if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
+ 'TimingSimpleCPU' in env['CPU_MODELS']:
+ DebugFlag('SimpleCPU')
+
if need_simple_base:
Source('base.cc')
+ SimObject('BaseSimpleCPU.py')