pwr: Adds logic to enter power gating for the cpu model

[gem5.git] / src / cpu / simple / SConscript

diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index c090a938c202edc03856f33929b87588e4f5b679..3b6b19c518052b136839866b5c74465a4a30abc1 100644 (file)
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -43,7 +43,8 @@ if 'TimingSimpleCPU' in env['CPU_MODELS']:
 
 if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
        'TimingSimpleCPU' in env['CPU_MODELS']:
-    TraceFlag('SimpleCPU')
+    DebugFlag('SimpleCPU')
 
 if need_simple_base:
     Source('base.cc')
+    SimObject('BaseSimpleCPU.py')