pwr: Adds logic to enter power gating for the cpu model

[gem5.git] / src / cpu / simple / SConscript

diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index ccccab2b5c2aa6ceb8b0b04529a989cad9356960..3b6b19c518052b136839866b5c74465a4a30abc1 100644 (file)
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -41,5 +41,10 @@ if 'TimingSimpleCPU' in env['CPU_MODELS']:
     SimObject('TimingSimpleCPU.py')
     Source('timing.cc')
 
+if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
+       'TimingSimpleCPU' in env['CPU_MODELS']:
+    DebugFlag('SimpleCPU')
+
 if need_simple_base:
     Source('base.cc')
+    SimObject('BaseSimpleCPU.py')