cpu: Add support for CMOs in the cpu models

[gem5.git] / src / cpu / simple / TimingSimpleCPU.py

diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 8d6888f72e653e2fefbf27cd7d4fcb833583ec98..25149eaa85bd6b35af31e70be63ebc38e6c85d1f 100644 (file)
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -31,6 +31,12 @@ from BaseSimpleCPU import BaseSimpleCPU
 
 class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
-    icache_port = Port("Instruction Port")
-    dcache_port = Port("Data Port")
-    _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port']
+    cxx_header = "cpu/simple/timing.hh"
+
+    @classmethod
+    def memory_mode(cls):
+        return 'timing'
+
+    @classmethod
+    def support_take_over(cls):
+        return True