pwr: Adds logic to enter power gating for the cpu model

[gem5.git] / src / cpu / simple / TimingSimpleCPU.py

diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 2fcde175ceadbe83d13445a447cbecb16eae6848..25149eaa85bd6b35af31e70be63ebc38e6c85d1f 100644 (file)
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -27,15 +27,16 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
-from BaseCPU import BaseCPU
+from BaseSimpleCPU import BaseSimpleCPU
 
-class TimingSimpleCPU(BaseCPU):
+class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
-    function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
-    icache_port = Port("Instruction Port")
-    dcache_port = Port("Data Port")
-    _mem_ports = ['icache_port', 'dcache_port']
+    cxx_header = "cpu/simple/timing.hh"
+
+    @classmethod
+    def memory_mode(cls):
+        return 'timing'
+
+    @classmethod
+    def support_take_over(cls):
+        return True