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pwr: Adds logic to enter power gating for the cpu model
[gem5.git]
/
src
/
cpu
/
simple
/
TimingSimpleCPU.py
diff --git
a/src/cpu/simple/TimingSimpleCPU.py
b/src/cpu/simple/TimingSimpleCPU.py
index 61491b0872ce7491af9fc4a1f52bfe18d234e6b0..25149eaa85bd6b35af31e70be63ebc38e6c85d1f 100644
(file)
--- a/
src/cpu/simple/TimingSimpleCPU.py
+++ b/
src/cpu/simple/TimingSimpleCPU.py
@@
-31,3
+31,12
@@
from BaseSimpleCPU import BaseSimpleCPU
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
+ cxx_header = "cpu/simple/timing.hh"
+
+ @classmethod
+ def memory_mode(cls):
+ return 'timing'
+
+ @classmethod
+ def support_take_over(cls):
+ return True