class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
- _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
+ cxx_header = "cpu/simple/timing.hh"
+
+ @classmethod
+ def memory_mode(cls):
+ return 'timing'
+
+ @classmethod
+ def support_take_over(cls):
+ return True