SE/FS: Expose the same methods on the CPUs in SE and FS modes.

[gem5.git] / src / cpu / simple / atomic.hh

diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 0edca936972c20e2f0e8b065cc55c4eedd4a453f..246afa0b2ba126e6bb428ea4a19b549abcc59a56 100644 (file)
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -32,34 +32,17 @@
 #define __CPU_SIMPLE_ATOMIC_HH__
 
 #include "cpu/simple/base.hh"
+#include "params/AtomicSimpleCPU.hh"
 
 class AtomicSimpleCPU : public BaseSimpleCPU
 {
   public:
 
-    struct Params : public BaseSimpleCPU::Params {
-        int width;
-        bool simulate_stalls;
-    };
-
-    AtomicSimpleCPU(Params *params);
+    AtomicSimpleCPU(AtomicSimpleCPUParams *params);
     virtual ~AtomicSimpleCPU();
 
     virtual void init();
 
-  public:
-    //
-    enum Status {
-        Running,
-        Idle,
-        SwitchedOut
-    };
-
-  protected:
-    Status _status;
-
-    Status status() const { return _status; }
-
   private:
 
     struct TickEvent : public Event
@@ -68,30 +51,33 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
         TickEvent(AtomicSimpleCPU *c);
         void process();
-        const char *description();
+        const char *description() const;
     };
 
     TickEvent tickEvent;
 
     const int width;
-    const bool simulate_stalls;
+    bool locked;
+    const bool simulate_data_stalls;
+    const bool simulate_inst_stalls;
 
     // main simulation loop (one cycle)
     void tick();
 
     class CpuPort : public Port
     {
-
-        AtomicSimpleCPU *cpu;
-
       public:
 
         CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
-            : Port(_name), cpu(_cpu)
+            : Port(_name, _cpu), cpu(_cpu)
         { }
 
+        bool snoopRangeSent;
+
       protected:
 
+        AtomicSimpleCPU *cpu;
+
         virtual bool recvTiming(PacketPtr pkt);
 
         virtual Tick recvAtomic(PacketPtr pkt);
@@ -103,23 +89,34 @@ class AtomicSimpleCPU : public BaseSimpleCPU
         virtual void recvRetry();
 
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
-            AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+            bool &snoop)
+        { resp.clear(); snoop = true; }
 
     };
     CpuPort icachePort;
-    CpuPort dcachePort;
 
-    Request  *ifetch_req;
-    PacketPtr ifetch_pkt;
-    Request  *data_read_req;
-    PacketPtr data_read_pkt;
-    Request  *data_write_req;
-    PacketPtr data_write_pkt;
+    class DcachePort : public CpuPort
+    {
+      public:
+        DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
+            : CpuPort(_name, _cpu)
+        { }
+
+        virtual void setPeer(Port *port);
+    };
+    DcachePort dcachePort;
+
+    CpuPort physmemPort;
+    bool hasPhysMemPort;
+    Request ifetch_req;
+    Request data_read_req;
+    Request data_write_req;
 
     bool dcache_access;
     Tick dcache_latency;
 
+    Range<Addr> physMemAddr;
+
   public:
 
     virtual Port *getPort(const std::string &if_name, int idx = -1);
@@ -134,11 +131,16 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     virtual void activateContext(int thread_num, int delay);
     virtual void suspendContext(int thread_num);
 
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+    /**
+     * Print state of address in memory system via PrintReq (for
+     * debugging).
+     */
+    void printAddr(Addr a);
 };
 
 #endif // __CPU_SIMPLE_ATOMIC_HH__