/*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2013,2015 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
#ifndef __CPU_SIMPLE_ATOMIC_HH__
#define __CPU_SIMPLE_ATOMIC_HH__
-#include "base/hashmap.hh"
#include "cpu/simple/base.hh"
+#include "cpu/simple/exec_context.hh"
+#include "mem/request.hh"
#include "params/AtomicSimpleCPU.hh"
-
-/**
- * Start and end address of basic block for SimPoint profiling.
- * This structure is used to look up the hash table of BBVs.
- * - first: PC of first inst in basic block
- * - second: PC of last inst in basic block
- */
-typedef std::pair<Addr, Addr> BasicBlockRange;
-
-/** Overload hash function for BasicBlockRange type */
-__hash_namespace_begin
-template <>
-struct hash<BasicBlockRange>
-{
- public:
- size_t operator()(const BasicBlockRange &bb) const {
- return hash<Addr>()(bb.first + bb.second);
- }
-};
-__hash_namespace_end
-
+#include "sim/probe/probe.hh"
class AtomicSimpleCPU : public BaseSimpleCPU
{
AtomicSimpleCPU(AtomicSimpleCPUParams *params);
virtual ~AtomicSimpleCPU();
- virtual void init();
+ void init() override;
private:
- struct TickEvent : public Event
- {
- AtomicSimpleCPU *cpu;
-
- TickEvent(AtomicSimpleCPU *c);
- void process();
- const char *description() const;
- };
-
- TickEvent tickEvent;
+ EventFunctionWrapper tickEvent;
const int width;
bool locked;
const bool simulate_data_stalls;
const bool simulate_inst_stalls;
- /**
- * Drain manager to use when signaling drain completion
- *
- * This pointer is non-NULL when draining and NULL otherwise.
- */
- DrainManager *drain_manager;
-
// main simulation loop (one cycle)
void tick();
* </ul>
*/
bool isDrained() {
- return microPC() == 0 &&
+ SimpleExecContext &t_info = *threadInfo[curThread];
+
+ return t_info.thread->microPC() == 0 &&
!locked &&
- !stayAtPC;
+ !t_info.stayAtPC;
}
/**
public:
- AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
+ AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
: MasterPort(_name, _cpu)
{ }
protected:
- virtual Tick recvAtomicSnoop(PacketPtr pkt)
- {
- // Snooping a coherence request, just return
- return 0;
- }
-
bool recvTimingResp(PacketPtr pkt)
{
panic("Atomic CPU doesn't expect recvTimingResp!\n");
return true;
}
- void recvRetry()
+ void recvReqRetry()
{
panic("Atomic CPU doesn't expect recvRetry!\n");
}
};
+ class AtomicCPUDPort : public AtomicCPUPort
+ {
+
+ public:
+
+ AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
+ : AtomicCPUPort(_name, _cpu), cpu(_cpu)
+ {
+ cacheBlockMask = ~(cpu->cacheLineSize() - 1);
+ }
+
+ bool isSnooping() const { return true; }
+
+ Addr cacheBlockMask;
+ protected:
+ BaseSimpleCPU *cpu;
+
+ virtual Tick recvAtomicSnoop(PacketPtr pkt);
+ virtual void recvFunctionalSnoop(PacketPtr pkt);
+ };
+
+
AtomicCPUPort icachePort;
- AtomicCPUPort dcachePort;
+ AtomicCPUDPort dcachePort;
bool fastmem;
Request ifetch_req;
bool dcache_access;
Tick dcache_latency;
- /**
- * Profile basic blocks for SimPoints.
- * Called at every macro inst to increment basic block inst counts and
- * to profile block if end of block.
- */
- void profileSimPoint();
-
- /** Data structures for SimPoints BBV generation
- * @{
- */
-
- /** Whether SimPoint BBV profiling is enabled */
- const bool simpoint;
- /** SimPoint profiling interval size in instructions */
- const uint64_t intervalSize;
-
- /** Inst count in current basic block */
- uint64_t intervalCount;
- /** Excess inst count from previous interval*/
- uint64_t intervalDrift;
- /** Pointer to SimPoint BBV output stream */
- std::ostream *simpointStream;
-
- /** Basic Block information */
- struct BBInfo {
- /** Unique ID */
- uint64_t id;
- /** Num of static insts in BB */
- uint64_t insts;
- /** Accumulated dynamic inst count executed by BB */
- uint64_t count;
- };
-
- /** Hash table containing all previously seen basic blocks */
- m5::hash_map<BasicBlockRange, BBInfo> bbMap;
- /** Currently executing basic block */
- BasicBlockRange currentBBV;
- /** inst count in current basic block */
- uint64_t currentBBVInstCount;
-
- /** @}
- * End of data structures for SimPoints BBV generation
- */
+ /** Probe Points. */
+ ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
protected:
/** Return a reference to the data port. */
- virtual MasterPort &getDataPort() { return dcachePort; }
+ MasterPort &getDataPort() override { return dcachePort; }
/** Return a reference to the instruction port. */
- virtual MasterPort &getInstPort() { return icachePort; }
+ MasterPort &getInstPort() override { return icachePort; }
+
+ /** Perform snoop for other cpu-local thread contexts. */
+ void threadSnoop(PacketPtr pkt, ThreadID sender);
public:
- unsigned int drain(DrainManager *drain_manager);
- void drainResume();
+ DrainState drain() override;
+ void drainResume() override;
- void switchOut();
- void takeOverFrom(BaseCPU *oldCPU);
+ void switchOut() override;
+ void takeOverFrom(BaseCPU *oldCPU) override;
- void verifyMemoryMode() const;
+ void verifyMemoryMode() const override;
- virtual void activateContext(ThreadID thread_num, Cycles delay);
- virtual void suspendContext(ThreadID thread_num);
+ void activateContext(ThreadID thread_num) override;
+ void suspendContext(ThreadID thread_num) override;
- Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size,
+ Request::Flags flags) override;
+
+ Fault initiateMemRead(Addr addr, unsigned size,
+ Request::Flags flags) override;
Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Addr addr, Request::Flags flags, uint64_t *res) override;
+
+ void regProbePoints() override;
/**
* Print state of address in memory system via PrintReq (for
projects / gem5.git / blobdiff