pwr: Adds logic to enter power gating for the cpu model

[gem5.git] / src / cpu / simple / atomic.hh

diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 76ee9f897463305394837d02640286b33661f86c..c9dd954bb098c669f955c063376ae7b90ddbf9fa 100644 (file)
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -45,6 +45,7 @@
 
 #include "cpu/simple/base.hh"
 #include "cpu/simple/exec_context.hh"
+#include "mem/request.hh"
 #include "params/AtomicSimpleCPU.hh"
 #include "sim/probe/probe.hh"
 
@@ -55,20 +56,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     AtomicSimpleCPU(AtomicSimpleCPUParams *params);
     virtual ~AtomicSimpleCPU();
 
-    virtual void init();
+    void init() override;
 
   private:
 
-    struct TickEvent : public Event
-    {
-        AtomicSimpleCPU *cpu;
-
-        TickEvent(AtomicSimpleCPU *c);
-        void process();
-        const char *description() const;
-    };
-
-    TickEvent tickEvent;
+    EventFunctionWrapper tickEvent;
 
     const int width;
     bool locked;
@@ -127,7 +119,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
         { }
 
       protected:
-        virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
 
         bool recvTimingResp(PacketPtr pkt)
         {
@@ -181,30 +172,37 @@ class AtomicSimpleCPU : public BaseSimpleCPU
   protected:
 
     /** Return a reference to the data port. */
-    virtual MasterPort &getDataPort() { return dcachePort; }
+    MasterPort &getDataPort() override { return dcachePort; }
 
     /** Return a reference to the instruction port. */
-    virtual MasterPort &getInstPort() { return icachePort; }
+    MasterPort &getInstPort() override { return icachePort; }
+
+    /** Perform snoop for other cpu-local thread contexts. */
+    void threadSnoop(PacketPtr pkt, ThreadID sender);
 
   public:
 
-    DrainState drain() M5_ATTR_OVERRIDE;
-    void drainResume() M5_ATTR_OVERRIDE;
+    DrainState drain() override;
+    void drainResume() override;
+
+    void switchOut() override;
+    void takeOverFrom(BaseCPU *oldCPU) override;
 
-    void switchOut();
-    void takeOverFrom(BaseCPU *oldCPU);
+    void verifyMemoryMode() const override;
 
-    void verifyMemoryMode() const;
+    void activateContext(ThreadID thread_num) override;
+    void suspendContext(ThreadID thread_num) override;
 
-    virtual void activateContext(ThreadID thread_num);
-    virtual void suspendContext(ThreadID thread_num);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size,
+                  Request::Flags flags) override;
 
-    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+    Fault initiateMemRead(Addr addr, unsigned size,
+                          Request::Flags flags) override;
 
     Fault writeMem(uint8_t *data, unsigned size,
-                   Addr addr, unsigned flags, uint64_t *res);
+                   Addr addr, Request::Flags flags, uint64_t *res) override;
 
-    virtual void regProbePoints();
+    void regProbePoints() override;
 
     /**
      * Print state of address in memory system via PrintReq (for