/*
+ * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Authors: Steve Reinhardt
*/
-#include "arch/faults.hh"
+#include "cpu/simple/base.hh"
+
+#include "arch/kernel_stats.hh"
+#include "arch/stacktrace.hh"
+#include "arch/tlb.hh"
#include "arch/utility.hh"
+#include "arch/vtophys.hh"
#include "base/cp_annotate.hh"
#include "base/cprintf.hh"
#include "base/inifile.hh"
#include "base/loader/symtab.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
#include "base/pollevent.hh"
-#include "base/range.hh"
-#include "base/stats/events.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
+#include "cpu/checker/cpu.hh"
+#include "cpu/checker/thread_context.hh"
#include "cpu/exetrace.hh"
+#include "cpu/pred/bpred_unit.hh"
#include "cpu/profile.hh"
-#include "cpu/simple/base.hh"
+#include "cpu/simple/exec_context.hh"
#include "cpu/simple_thread.hh"
#include "cpu/smt.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/Decode.hh"
+#include "debug/Fetch.hh"
+#include "debug/Quiesce.hh"
+#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/BaseSimpleCPU.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
+#include "sim/faults.hh"
+#include "sim/full_system.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "arch/stacktrace.hh"
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
-#include "base/remote_gdb.hh"
-#else // !FULL_SYSTEM
-#include "mem/mem_object.hh"
-#endif // FULL_SYSTEM
-
using namespace std;
using namespace TheISA;
BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
- : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
+ : BaseCPU(p),
+ curThread(0),
+ branchPred(p->branchPred),
+ traceData(NULL),
+ inst(),
+ _status(Idle)
{
-#if FULL_SYSTEM
- thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
-#else
- thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
- p->itb, p->dtb);
-#endif // !FULL_SYSTEM
-
- thread->setStatus(ThreadContext::Halted);
-
- tc = thread->getTC();
-
- numInst = 0;
- startNumInst = 0;
- numLoad = 0;
- startNumLoad = 0;
- lastIcacheStall = 0;
- lastDcacheStall = 0;
+ SimpleThread *thread;
- threadContexts.push_back(tc);
+ for (unsigned i = 0; i < numThreads; i++) {
+ if (FullSystem) {
+ thread = new SimpleThread(this, i, p->system,
+ p->itb, p->dtb, p->isa[i]);
+ } else {
+ thread = new SimpleThread(this, i, p->system, p->workload[i],
+ p->itb, p->dtb, p->isa[i]);
+ }
+ threadInfo.push_back(new SimpleExecContext(this, thread));
+ ThreadContext *tc = thread->getTC();
+ threadContexts.push_back(tc);
+ }
+ if (p->checker) {
+ if (numThreads != 1)
+ fatal("Checker currently does not support SMT");
- fetchOffset = 0;
- stayAtPC = false;
+ BaseCPU *temp_checker = p->checker;
+ checker = dynamic_cast<CheckerCPU *>(temp_checker);
+ checker->setSystem(p->system);
+ // Manipulate thread context
+ ThreadContext *cpu_tc = threadContexts[0];
+ threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
+ } else {
+ checker = NULL;
+ }
}
-BaseSimpleCPU::~BaseSimpleCPU()
+void
+BaseSimpleCPU::init()
{
+ BaseCPU::init();
+
+ for (auto tc : threadContexts) {
+ // Initialise the ThreadContext's memory proxies
+ tc->initMemProxies(tc);
+
+ if (FullSystem && !params()->switched_out) {
+ // initialize CPU, including PC
+ TheISA::initCPU(tc, tc->contextId());
+ }
+ }
}
void
-BaseSimpleCPU::deallocateContext(int thread_num)
+BaseSimpleCPU::checkPcEventQueue()
{
- // for now, these are equivalent
- suspendContext(thread_num);
+ Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
+ do {
+ oldpc = pc;
+ system->pcEventQueue.service(threadContexts[curThread]);
+ pc = threadInfo[curThread]->thread->instAddr();
+ } while (oldpc != pc);
}
-
void
-BaseSimpleCPU::haltContext(int thread_num)
+BaseSimpleCPU::swapActiveThread()
{
- // for now, these are equivalent
- suspendContext(thread_num);
+ if (numThreads > 1) {
+ if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
+ !threadInfo[curThread]->stayAtPC) {
+ // Swap active threads
+ if (!activeThreads.empty()) {
+ curThread = activeThreads.front();
+ activeThreads.pop_front();
+ activeThreads.push_back(curThread);
+ }
+ }
+ }
}
-
void
-BaseSimpleCPU::regStats()
+BaseSimpleCPU::countInst()
{
- using namespace Stats;
+ SimpleExecContext& t_info = *threadInfo[curThread];
- BaseCPU::regStats();
+ if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
+ t_info.numInst++;
+ t_info.numInsts++;
+ }
+ t_info.numOp++;
+ t_info.numOps++;
- numInsts
- .name(name() + ".num_insts")
- .desc("Number of instructions executed")
- ;
-
- numMemRefs
- .name(name() + ".num_refs")
- .desc("Number of memory references")
- ;
-
- notIdleFraction
- .name(name() + ".not_idle_fraction")
- .desc("Percentage of non-idle cycles")
- ;
-
- idleFraction
- .name(name() + ".idle_fraction")
- .desc("Percentage of idle cycles")
- ;
-
- icacheStallCycles
- .name(name() + ".icache_stall_cycles")
- .desc("ICache total stall cycles")
- .prereq(icacheStallCycles)
- ;
-
- dcacheStallCycles
- .name(name() + ".dcache_stall_cycles")
- .desc("DCache total stall cycles")
- .prereq(dcacheStallCycles)
- ;
-
- icacheRetryCycles
- .name(name() + ".icache_retry_cycles")
- .desc("ICache total retry cycles")
- .prereq(icacheRetryCycles)
- ;
-
- dcacheRetryCycles
- .name(name() + ".dcache_retry_cycles")
- .desc("DCache total retry cycles")
- .prereq(dcacheRetryCycles)
- ;
-
- idleFraction = constant(1.0) - notIdleFraction;
+ system->totalNumInsts++;
+ t_info.thread->funcExeInst++;
}
-void
-BaseSimpleCPU::resetStats()
+Counter
+BaseSimpleCPU::totalInsts() const
{
-// startNumInst = numInst;
- notIdleFraction = (_status != Idle);
+ Counter total_inst = 0;
+ for (auto& t_info : threadInfo) {
+ total_inst += t_info->numInst;
+ }
+
+ return total_inst;
}
-void
-BaseSimpleCPU::serialize(ostream &os)
+Counter
+BaseSimpleCPU::totalOps() const
{
- SERIALIZE_ENUM(_status);
- BaseCPU::serialize(os);
-// SERIALIZE_SCALAR(inst);
- nameOut(os, csprintf("%s.xc.0", name()));
- thread->serialize(os);
+ Counter total_op = 0;
+ for (auto& t_info : threadInfo) {
+ total_op += t_info->numOp;
+ }
+
+ return total_op;
}
-void
-BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
+BaseSimpleCPU::~BaseSimpleCPU()
{
- UNSERIALIZE_ENUM(_status);
- BaseCPU::unserialize(cp, section);
-// UNSERIALIZE_SCALAR(inst);
- thread->unserialize(cp, csprintf("%s.xc.0", section));
}
void
-change_thread_state(ThreadID tid, int activate, int priority)
+BaseSimpleCPU::haltContext(ThreadID thread_num)
{
+ // for now, these are equivalent
+ suspendContext(thread_num);
+ updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
}
+
void
-BaseSimpleCPU::prefetch(Addr addr, unsigned flags)
+BaseSimpleCPU::regStats()
{
- if (traceData) {
- traceData->setAddr(addr);
- }
+ using namespace Stats;
- // need to do this...
+ BaseCPU::regStats();
+
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
+ SimpleExecContext& t_info = *threadInfo[tid];
+
+ std::string thread_str = name();
+ if (numThreads > 1)
+ thread_str += ".thread" + std::to_string(tid);
+
+ t_info.numInsts
+ .name(thread_str + ".committedInsts")
+ .desc("Number of instructions committed")
+ ;
+
+ t_info.numOps
+ .name(thread_str + ".committedOps")
+ .desc("Number of ops (including micro ops) committed")
+ ;
+
+ t_info.numIntAluAccesses
+ .name(thread_str + ".num_int_alu_accesses")
+ .desc("Number of integer alu accesses")
+ ;
+
+ t_info.numFpAluAccesses
+ .name(thread_str + ".num_fp_alu_accesses")
+ .desc("Number of float alu accesses")
+ ;
+
+ t_info.numVecAluAccesses
+ .name(thread_str + ".num_vec_alu_accesses")
+ .desc("Number of vector alu accesses")
+ ;
+
+ t_info.numCallsReturns
+ .name(thread_str + ".num_func_calls")
+ .desc("number of times a function call or return occured")
+ ;
+
+ t_info.numCondCtrlInsts
+ .name(thread_str + ".num_conditional_control_insts")
+ .desc("number of instructions that are conditional controls")
+ ;
+
+ t_info.numIntInsts
+ .name(thread_str + ".num_int_insts")
+ .desc("number of integer instructions")
+ ;
+
+ t_info.numFpInsts
+ .name(thread_str + ".num_fp_insts")
+ .desc("number of float instructions")
+ ;
+
+ t_info.numVecInsts
+ .name(thread_str + ".num_vec_insts")
+ .desc("number of vector instructions")
+ ;
+
+ t_info.numIntRegReads
+ .name(thread_str + ".num_int_register_reads")
+ .desc("number of times the integer registers were read")
+ ;
+
+ t_info.numIntRegWrites
+ .name(thread_str + ".num_int_register_writes")
+ .desc("number of times the integer registers were written")
+ ;
+
+ t_info.numFpRegReads
+ .name(thread_str + ".num_fp_register_reads")
+ .desc("number of times the floating registers were read")
+ ;
+
+ t_info.numFpRegWrites
+ .name(thread_str + ".num_fp_register_writes")
+ .desc("number of times the floating registers were written")
+ ;
+
+ t_info.numVecRegReads
+ .name(thread_str + ".num_vec_register_reads")
+ .desc("number of times the vector registers were read")
+ ;
+
+ t_info.numVecRegWrites
+ .name(thread_str + ".num_vec_register_writes")
+ .desc("number of times the vector registers were written")
+ ;
+
+ t_info.numCCRegReads
+ .name(thread_str + ".num_cc_register_reads")
+ .desc("number of times the CC registers were read")
+ .flags(nozero)
+ ;
+
+ t_info.numCCRegWrites
+ .name(thread_str + ".num_cc_register_writes")
+ .desc("number of times the CC registers were written")
+ .flags(nozero)
+ ;
+
+ t_info.numMemRefs
+ .name(thread_str + ".num_mem_refs")
+ .desc("number of memory refs")
+ ;
+
+ t_info.numStoreInsts
+ .name(thread_str + ".num_store_insts")
+ .desc("Number of store instructions")
+ ;
+
+ t_info.numLoadInsts
+ .name(thread_str + ".num_load_insts")
+ .desc("Number of load instructions")
+ ;
+
+ t_info.notIdleFraction
+ .name(thread_str + ".not_idle_fraction")
+ .desc("Percentage of non-idle cycles")
+ ;
+
+ t_info.idleFraction
+ .name(thread_str + ".idle_fraction")
+ .desc("Percentage of idle cycles")
+ ;
+
+ t_info.numBusyCycles
+ .name(thread_str + ".num_busy_cycles")
+ .desc("Number of busy cycles")
+ ;
+
+ t_info.numIdleCycles
+ .name(thread_str + ".num_idle_cycles")
+ .desc("Number of idle cycles")
+ ;
+
+ t_info.icacheStallCycles
+ .name(thread_str + ".icache_stall_cycles")
+ .desc("ICache total stall cycles")
+ .prereq(t_info.icacheStallCycles)
+ ;
+
+ t_info.dcacheStallCycles
+ .name(thread_str + ".dcache_stall_cycles")
+ .desc("DCache total stall cycles")
+ .prereq(t_info.dcacheStallCycles)
+ ;
+
+ t_info.statExecutedInstType
+ .init(Enums::Num_OpClass)
+ .name(thread_str + ".op_class")
+ .desc("Class of executed instruction")
+ .flags(total | pdf | dist)
+ ;
+
+ for (unsigned i = 0; i < Num_OpClasses; ++i) {
+ t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
+ }
+
+ t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
+ t_info.numIdleCycles = t_info.idleFraction * numCycles;
+ t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
+
+ t_info.numBranches
+ .name(thread_str + ".Branches")
+ .desc("Number of branches fetched")
+ .prereq(t_info.numBranches);
+
+ t_info.numPredictedBranches
+ .name(thread_str + ".predictedBranches")
+ .desc("Number of branches predicted as taken")
+ .prereq(t_info.numPredictedBranches);
+
+ t_info.numBranchMispred
+ .name(thread_str + ".BranchMispred")
+ .desc("Number of branch mispredictions")
+ .prereq(t_info.numBranchMispred);
+ }
}
void
-BaseSimpleCPU::writeHint(Addr addr, int size, unsigned flags)
+BaseSimpleCPU::resetStats()
{
- if (traceData) {
- traceData->setAddr(addr);
+ for (auto &thread_info : threadInfo) {
+ thread_info->notIdleFraction = (_status != Idle);
}
-
- // need to do this...
}
-
-Fault
-BaseSimpleCPU::copySrcTranslate(Addr src)
+void
+BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
{
-#if 0
- static bool no_warn = true;
- unsigned blk_size =
- (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
- // Only support block sizes of 64 atm.
- assert(blk_size == 64);
- int offset = src & (blk_size - 1);
-
- // Make sure block doesn't span page
- if (no_warn &&
- (src & PageMask) != ((src + blk_size) & PageMask) &&
- (src >> 40) != 0xfffffc) {
- warn("Copied block source spans pages %x.", src);
- no_warn = false;
- }
-
- memReq->reset(src & ~(blk_size - 1), blk_size);
-
- // translate to physical address
- Fault fault = thread->translateDataReadReq(req);
+ assert(_status == Idle || _status == Running);
- if (fault == NoFault) {
- thread->copySrcAddr = src;
- thread->copySrcPhysAddr = memReq->paddr + offset;
- } else {
- assert(!fault->isAlignmentFault());
-
- thread->copySrcAddr = 0;
- thread->copySrcPhysAddr = 0;
- }
- return fault;
-#else
- return NoFault;
-#endif
+ threadInfo[tid]->thread->serialize(cp);
}
-Fault
-BaseSimpleCPU::copy(Addr dest)
+void
+BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
{
-#if 0
- static bool no_warn = true;
- unsigned blk_size =
- (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
- // Only support block sizes of 64 atm.
- assert(blk_size == 64);
- uint8_t data[blk_size];
- //assert(thread->copySrcAddr);
- int offset = dest & (blk_size - 1);
-
- // Make sure block doesn't span page
- if (no_warn &&
- (dest & PageMask) != ((dest + blk_size) & PageMask) &&
- (dest >> 40) != 0xfffffc) {
- no_warn = false;
- warn("Copied block destination spans pages %x. ", dest);
- }
+ threadInfo[tid]->thread->unserialize(cp);
+}
- memReq->reset(dest & ~(blk_size -1), blk_size);
- // translate to physical address
- Fault fault = thread->translateDataWriteReq(req);
-
- if (fault == NoFault) {
- Addr dest_addr = memReq->paddr + offset;
- // Need to read straight from memory since we have more than 8 bytes.
- memReq->paddr = thread->copySrcPhysAddr;
- thread->mem->read(memReq, data);
- memReq->paddr = dest_addr;
- thread->mem->write(memReq, data);
- if (dcacheInterface) {
- memReq->cmd = Copy;
- memReq->completionEvent = NULL;
- memReq->paddr = thread->copySrcPhysAddr;
- memReq->dest = dest_addr;
- memReq->size = 64;
- memReq->time = curTick;
- dcacheInterface->access(memReq);
- }
- }
- else
- assert(!fault->isAlignmentFault());
-
- return fault;
-#else
- panic("copy not implemented");
- return NoFault;
-#endif
+void
+change_thread_state(ThreadID tid, int activate, int priority)
+{
}
-#if FULL_SYSTEM
Addr
BaseSimpleCPU::dbg_vtophys(Addr addr)
{
- return vtophys(tc, addr);
+ return vtophys(threadContexts[curThread], addr);
}
-#endif // FULL_SYSTEM
-#if FULL_SYSTEM
void
-BaseSimpleCPU::wakeup()
+BaseSimpleCPU::wakeup(ThreadID tid)
{
- if (thread->status() != ThreadContext::Suspended)
- return;
+ getCpuAddrMonitor(tid)->gotWakeup = true;
- DPRINTF(Quiesce,"Suspended Processor awoke\n");
- thread->activate();
+ if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
+ DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
+ threadInfo[tid]->thread->activate();
+ }
}
-#endif // FULL_SYSTEM
void
BaseSimpleCPU::checkForInterrupts()
{
-#if FULL_SYSTEM
+ SimpleExecContext&t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+ ThreadContext* tc = thread->getTC();
+
if (checkInterrupts(tc)) {
- Fault interrupt = interrupts->getInterrupt(tc);
+ Fault interrupt = interrupts[curThread]->getInterrupt(tc);
if (interrupt != NoFault) {
- predecoder.reset();
- interrupts->updateIntrInfo(tc);
+ t_info.fetchOffset = 0;
+ interrupts[curThread]->updateIntrInfo(tc);
interrupt->invoke(tc);
+ thread->decoder.reset();
}
}
-#endif
}
void
BaseSimpleCPU::setupFetchRequest(Request *req)
{
- Addr threadPC = thread->readPC();
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
+ Addr instAddr = thread->instAddr();
+ Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
// set up memory request for instruction fetch
-#if ISA_HAS_DELAY_SLOT
- DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
- thread->readNextPC(),thread->readNextNPC());
-#else
- DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
- thread->readNextPC());
-#endif
-
- Addr fetchPC = (threadPC & PCMask) + fetchOffset;
- req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC);
+ DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
+
+ req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
+ instMasterId(), instAddr);
}
void
BaseSimpleCPU::preExecute()
{
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
#if THE_ISA == ALPHA_ISA
#endif // ALPHA_ISA
// check for instruction-count-based events
- comInstEventQueue[0]->serviceEvents(numInst);
+ comInstEventQueue[curThread]->serviceEvents(t_info.numInst);
+ system->instEventQueue.serviceEvents(system->totalNumInsts);
// decode the instruction
inst = gtoh(inst);
- MicroPC upc = thread->readMicroPC();
+ TheISA::PCState pcState = thread->pcState();
- if (isRomMicroPC(upc)) {
- stayAtPC = false;
- curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst);
+ if (isRomMicroPC(pcState.microPC())) {
+ t_info.stayAtPC = false;
+ curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
+ curMacroStaticInst);
} else if (!curMacroStaticInst) {
//We're not in the middle of a macro instruction
StaticInstPtr instPtr = NULL;
+ TheISA::Decoder *decoder = &(thread->decoder);
+
//Predecode, ie bundle up an ExtMachInst
- //This should go away once the constructor can be set up properly
- predecoder.setTC(thread->getTC());
//If more fetch data is needed, pass it in.
- Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
- //if(predecoder.needMoreBytes())
- predecoder.moreBytes(thread->readPC(), fetchPC, inst);
+ Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
+ //if (decoder->needMoreBytes())
+ decoder->moreBytes(pcState, fetchPC, inst);
//else
- // predecoder.process();
+ // decoder->process();
- //If an instruction is ready, decode it. Otherwise, we'll have to
+ //Decode an instruction if one is ready. Otherwise, we'll have to
//fetch beyond the MachInst at the current pc.
- if (predecoder.extMachInstReady()) {
-#if THE_ISA == X86_ISA
- thread->setNextPC(thread->readPC() + predecoder.getInstSize());
-#endif // X86_ISA
- stayAtPC = false;
- instPtr = StaticInst::decode(predecoder.getExtMachInst(),
- thread->readPC());
+ instPtr = decoder->decode(pcState);
+ if (instPtr) {
+ t_info.stayAtPC = false;
+ thread->pcState(pcState);
} else {
- stayAtPC = true;
- fetchOffset += sizeof(MachInst);
+ t_info.stayAtPC = true;
+ t_info.fetchOffset += sizeof(MachInst);
}
//If we decoded an instruction and it's microcoded, start pulling
//out micro ops
if (instPtr && instPtr->isMacroop()) {
curMacroStaticInst = instPtr;
- curStaticInst = curMacroStaticInst->fetchMicroop(upc);
+ curStaticInst =
+ curMacroStaticInst->fetchMicroop(pcState.microPC());
} else {
curStaticInst = instPtr;
}
} else {
//Read the next micro op from the macro op
- curStaticInst = curMacroStaticInst->fetchMicroop(upc);
+ curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
}
//If we decoded an instruction this "tick", record information about it.
- if(curStaticInst)
- {
+ if (curStaticInst) {
#if TRACING_ON
- traceData = tracer->getInstRecord(curTick, tc,
- curStaticInst, thread->readPC(),
- curMacroStaticInst, thread->readMicroPC());
+ traceData = tracer->getInstRecord(curTick(), thread->getTC(),
+ curStaticInst, thread->pcState(), curMacroStaticInst);
- DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
+ DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
curStaticInst->getName(), curStaticInst->machInst);
#endif // TRACING_ON
+ }
-#if FULL_SYSTEM
- thread->setInst(inst);
-#endif // FULL_SYSTEM
+ if (branchPred && curStaticInst &&
+ curStaticInst->isControl()) {
+ // Use a fake sequence number since we only have one
+ // instruction in flight at the same time.
+ const InstSeqNum cur_sn(0);
+ t_info.predPC = thread->pcState();
+ const bool predict_taken(
+ branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
+ curThread));
+
+ if (predict_taken)
+ ++t_info.numPredictedBranches;
}
}
void
BaseSimpleCPU::postExecute()
{
-#if FULL_SYSTEM
- if (thread->profile && curStaticInst) {
- bool usermode = TheISA::inUserMode(tc);
- thread->profilePC = usermode ? 1 : thread->readPC();
- ProfileNode *node = thread->profile->consume(tc, curStaticInst);
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
+ assert(curStaticInst);
+
+ TheISA::PCState pc = threadContexts[curThread]->pcState();
+ Addr instAddr = pc.instAddr();
+ if (FullSystem && thread->profile) {
+ bool usermode = TheISA::inUserMode(threadContexts[curThread]);
+ thread->profilePC = usermode ? 1 : instAddr;
+ ProfileNode *node = thread->profile->consume(threadContexts[curThread],
+ curStaticInst);
if (node)
thread->profileNode = node;
}
-#endif
if (curStaticInst->isMemRef()) {
- numMemRefs++;
+ t_info.numMemRefs++;
}
if (curStaticInst->isLoad()) {
- ++numLoad;
- comLoadEventQueue[0]->serviceEvents(numLoad);
+ ++t_info.numLoad;
+ comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad);
}
if (CPA::available()) {
- CPA::cpa()->swAutoBegin(tc, thread->readNextPC());
+ CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
+ }
+
+ if (curStaticInst->isControl()) {
+ ++t_info.numBranches;
+ }
+
+ /* Power model statistics */
+ //integer alu accesses
+ if (curStaticInst->isInteger()){
+ t_info.numIntAluAccesses++;
+ t_info.numIntInsts++;
}
- traceFunctions(thread->readPC());
+ //float alu accesses
+ if (curStaticInst->isFloating()){
+ t_info.numFpAluAccesses++;
+ t_info.numFpInsts++;
+ }
+
+ //vector alu accesses
+ if (curStaticInst->isVector()){
+ t_info.numVecAluAccesses++;
+ t_info.numVecInsts++;
+ }
+
+ //number of function calls/returns to get window accesses
+ if (curStaticInst->isCall() || curStaticInst->isReturn()){
+ t_info.numCallsReturns++;
+ }
+
+ //the number of branch predictions that will be made
+ if (curStaticInst->isCondCtrl()){
+ t_info.numCondCtrlInsts++;
+ }
+
+ //result bus acceses
+ if (curStaticInst->isLoad()){
+ t_info.numLoadInsts++;
+ }
+
+ if (curStaticInst->isStore()){
+ t_info.numStoreInsts++;
+ }
+ /* End power model statistics */
+
+ t_info.statExecutedInstType[curStaticInst->opClass()]++;
+
+ if (FullSystem)
+ traceFunctions(instAddr);
if (traceData) {
traceData->dump();
delete traceData;
traceData = NULL;
}
-}
+ // Call CPU instruction commit probes
+ probeInstCommit(curStaticInst);
+}
void
-BaseSimpleCPU::advancePC(Fault fault)
+BaseSimpleCPU::advancePC(const Fault &fault)
{
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
+ const bool branching(thread->pcState().branching());
+
//Since we're moving to a new pc, zero out the offset
- fetchOffset = 0;
+ t_info.fetchOffset = 0;
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
- predecoder.reset();
- fault->invoke(tc);
+ fault->invoke(threadContexts[curThread], curStaticInst);
+ thread->decoder.reset();
} else {
- //If we're at the last micro op for this instruction
- if (curStaticInst && curStaticInst->isLastMicroop()) {
- //We should be working with a macro op or be in the ROM
- assert(curMacroStaticInst ||
- isRomMicroPC(thread->readMicroPC()));
- //Close out this macro op, and clean up the
- //microcode state
- curMacroStaticInst = StaticInst::nullStaticInstPtr;
- thread->setMicroPC(normalMicroPC(0));
- thread->setNextMicroPC(normalMicroPC(1));
+ if (curStaticInst) {
+ if (curStaticInst->isLastMicroop())
+ curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ TheISA::PCState pcState = thread->pcState();
+ TheISA::advancePC(pcState, curStaticInst);
+ thread->pcState(pcState);
}
- //If we're still in a macro op
- if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) {
- //Advance the micro pc
- thread->setMicroPC(thread->readNextMicroPC());
- //Advance the "next" micro pc. Note that there are no delay
- //slots, and micro ops are "word" addressed.
- thread->setNextMicroPC(thread->readNextMicroPC() + 1);
+ }
+
+ if (branchPred && curStaticInst && curStaticInst->isControl()) {
+ // Use a fake sequence number since we only have one
+ // instruction in flight at the same time.
+ const InstSeqNum cur_sn(0);
+
+ if (t_info.predPC == thread->pcState()) {
+ // Correctly predicted branch
+ branchPred->update(cur_sn, curThread);
} else {
- // go to the next instruction
- thread->setPC(thread->readNextPC());
- thread->setNextPC(thread->readNextNPC());
- thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
- assert(thread->readNextPC() != thread->readNextNPC());
+ // Mis-predicted branch
+ branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
+ ++t_info.numBranchMispred;
}
}
}
-/*Fault
-BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
+void
+BaseSimpleCPU::startup()
{
- // translate to physical address
- Fault fault = NoFault;
- int CacheID = Op & 0x3; // Lower 3 bits identify Cache
- int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
- if(CacheID > 1)
- {
- warn("CacheOps not implemented for secondary/tertiary caches\n");
- }
- else
- {
- switch(CacheOP)
- { // Fill Packet Type
- case 0: warn("Invalidate Cache Op\n");
- break;
- case 1: warn("Index Load Tag Cache Op\n");
- break;
- case 2: warn("Index Store Tag Cache Op\n");
- break;
- case 4: warn("Hit Invalidate Cache Op\n");
- break;
- case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
- break;
- case 6: warn("Hit Writeback\n");
- break;
- case 7: warn("Fetch & Lock Cache Op\n");
- break;
- default: warn("Unimplemented Cache Op\n");
- }
- }
- return fault;
-}*/
+ BaseCPU::startup();
+ for (auto& t_info : threadInfo)
+ t_info->thread->startup();
+}
projects / gem5.git / blobdiff