x86,misc: add additional info on faulting X86 instruction, fetched PC

[gem5.git] / src / cpu / simple / base.cc

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 673cadd77bf6c34d87fbdae00d2cbcbfa39c30dc..1f12afbf06a52b866d6335ebf657664701981891 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012,2015 ARM Limited
+ * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -41,21 +41,22 @@
  * Authors: Steve Reinhardt
  */
 
+#include "cpu/simple/base.hh"
+
 #include "arch/kernel_stats.hh"
 #include "arch/stacktrace.hh"
 #include "arch/tlb.hh"
 #include "arch/utility.hh"
 #include "arch/vtophys.hh"
-#include "base/loader/symtab.hh"
 #include "base/cp_annotate.hh"
 #include "base/cprintf.hh"
 #include "base/inifile.hh"
-#include "base/misc.hh"
+#include "base/loader/symtab.hh"
+#include "base/logging.hh"
 #include "base/pollevent.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
-#include "cpu/simple/base.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/checker/thread_context.hh"
@@ -214,6 +215,7 @@ BaseSimpleCPU::haltContext(ThreadID thread_num)
 {
     // for now, these are equivalent
     suspendContext(thread_num);
+    updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
 }
 
 
@@ -251,6 +253,11 @@ BaseSimpleCPU::regStats()
             .desc("Number of float alu accesses")
             ;
 
+        t_info.numVecAluAccesses
+            .name(thread_str + ".num_vec_alu_accesses")
+            .desc("Number of vector alu accesses")
+            ;
+
         t_info.numCallsReturns
             .name(thread_str + ".num_func_calls")
             .desc("number of times a function call or return occured")
@@ -271,6 +278,11 @@ BaseSimpleCPU::regStats()
             .desc("number of float instructions")
             ;
 
+        t_info.numVecInsts
+            .name(thread_str + ".num_vec_insts")
+            .desc("number of vector instructions")
+            ;
+
         t_info.numIntRegReads
             .name(thread_str + ".num_int_register_reads")
             .desc("number of times the integer registers were read")
@@ -291,6 +303,16 @@ BaseSimpleCPU::regStats()
             .desc("number of times the floating registers were written")
             ;
 
+        t_info.numVecRegReads
+            .name(thread_str + ".num_vec_register_reads")
+            .desc("number of times the vector registers were read")
+            ;
+
+        t_info.numVecRegWrites
+            .name(thread_str + ".num_vec_register_writes")
+            .desc("number of times the vector registers were written")
+            ;
+
         t_info.numCCRegReads
             .name(thread_str + ".num_cc_register_reads")
             .desc("number of times the CC registers were read")
@@ -416,15 +438,13 @@ BaseSimpleCPU::dbg_vtophys(Addr addr)
 }
 
 void
-BaseSimpleCPU::wakeup()
+BaseSimpleCPU::wakeup(ThreadID tid)
 {
-    getCpuAddrMonitor()->gotWakeup = true;
+    getCpuAddrMonitor(tid)->gotWakeup = true;
 
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
-        if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
-            DPRINTF(Quiesce,"Suspended Processor awoke\n");
-            threadInfo[tid]->thread->activate();
-        }
+    if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
+        DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
+        threadInfo[tid]->thread->activate();
     }
 }
 
@@ -436,11 +456,11 @@ BaseSimpleCPU::checkForInterrupts()
     ThreadContext* tc = thread->getTC();
 
     if (checkInterrupts(tc)) {
-        Fault interrupt = interrupts->getInterrupt(tc);
+        Fault interrupt = interrupts[curThread]->getInterrupt(tc);
 
         if (interrupt != NoFault) {
             t_info.fetchOffset = 0;
-            interrupts->updateIntrInfo(tc);
+            interrupts[curThread]->updateIntrInfo(tc);
             interrupt->invoke(tc);
             thread->decoder.reset();
         }
@@ -455,13 +475,13 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
     SimpleThread* thread = t_info.thread;
 
     Addr instAddr = thread->instAddr();
+    Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
 
     // set up memory request for instruction fetch
-    DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
+    DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
 
-    Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
-    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
-            instAddr);
+    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
+                 instMasterId(), instAddr);
 }
 
 
@@ -499,7 +519,7 @@ BaseSimpleCPU::preExecute()
         //Predecode, ie bundle up an ExtMachInst
         //If more fetch data is needed, pass it in.
         Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
-        //if(decoder->needMoreBytes())
+        //if (decoder->needMoreBytes())
             decoder->moreBytes(pcState, fetchPC, inst);
         //else
         //    decoder->process();
@@ -604,6 +624,12 @@ BaseSimpleCPU::postExecute()
         t_info.numFpInsts++;
     }
 
+    //vector alu accesses
+    if (curStaticInst->isVector()){
+        t_info.numVecAluAccesses++;
+        t_info.numVecInsts++;
+    }
+
     //number of function calls/returns to get window accesses
     if (curStaticInst->isCall() || curStaticInst->isReturn()){
         t_info.numCallsReturns++;