#include "mem/port.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
+#include "sim/system.hh"
// forward declarations
#if FULL_SYSTEM
class InstRecord;
}
+class BaseSimpleCPUParams;
+
class BaseSimpleCPU : public BaseCPU
{
protected:
Trace::InstRecord *traceData;
+ inline void checkPcEventQueue() {
+ Addr oldpc;
+ do {
+ oldpc = thread->readPC();
+ system->pcEventQueue.service(tc);
+ } while (oldpc != thread->readPC());
+ }
+
public:
void post_interrupt(int int_num, int index);
};
public:
- struct Params : public BaseCPU::Params
- {
- TheISA::ITB *itb;
- TheISA::DTB *dtb;
-#if !FULL_SYSTEM
- Process *process;
-#endif
- };
- BaseSimpleCPU(Params *params);
+ BaseSimpleCPU(BaseSimpleCPUParams *params);
virtual ~BaseSimpleCPU();
public:
protected:
int cpuId;
+ enum Status {
+ Idle,
+ Running,
+ IcacheRetry,
+ IcacheWaitResponse,
+ IcacheWaitSwitch,
+ DcacheRetry,
+ DcacheWaitResponse,
+ DcacheWaitSwitch,
+ SwitchedOut
+ };
+
+ Status _status;
+
public:
#if FULL_SYSTEM
return thread->setMiscReg(reg_idx, val);
}
+ void demapPage(Addr vaddr, uint64_t asn)
+ {
+ thread->demapPage(vaddr, asn);
+ }
+
+ void demapInstPage(Addr vaddr, uint64_t asn)
+ {
+ thread->demapInstPage(vaddr, asn);
+ }
+
+ void demapDataPage(Addr vaddr, uint64_t asn)
+ {
+ thread->demapDataPage(vaddr, asn);
+ }
+
unsigned readStCondFailures() {
return thread->readStCondFailures();
}