Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done...

[gem5.git] / src / cpu / simple / base.hh

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b25790e9234ce8e3940d3c277c3de06466e78f4d..aeae1a3d81e0913a58791657eaaf027eb0d48b6e 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -44,6 +44,7 @@
 #include "mem/port.hh"
 #include "mem/request.hh"
 #include "sim/eventq.hh"
+#include "sim/system.hh"
 
 // forward declarations
 #if FULL_SYSTEM
@@ -75,6 +76,8 @@ namespace Trace {
     class InstRecord;
 }
 
+class BaseSimpleCPUParams;
+
 
 class BaseSimpleCPU : public BaseCPU
 {
@@ -86,6 +89,14 @@ class BaseSimpleCPU : public BaseCPU
   protected:
     Trace::InstRecord *traceData;
 
+    inline void checkPcEventQueue() {
+        Addr oldpc;
+        do {
+            oldpc = thread->readPC();
+            system->pcEventQueue.service(tc);
+        } while (oldpc != thread->readPC());
+    }
+
   public:
     void post_interrupt(int int_num, int index);
 
@@ -98,16 +109,7 @@ class BaseSimpleCPU : public BaseCPU
     };
 
   public:
-    struct Params : public BaseCPU::Params
-    {
-#if FULL_SYSTEM
-        TheISA::ITB *itb;
-        TheISA::DTB *dtb;
-#else
-        Process *process;
-#endif
-    };
-    BaseSimpleCPU(Params *params);
+    BaseSimpleCPU(BaseSimpleCPUParams *params);
     virtual ~BaseSimpleCPU();
 
   public:
@@ -118,6 +120,24 @@ class BaseSimpleCPU : public BaseCPU
      * objects to modify this thread's state.
      */
     ThreadContext *tc;
+  protected:
+    int cpuId;
+
+    enum Status {
+        Idle,
+        Running,
+        IcacheRetry,
+        IcacheWaitResponse,
+        IcacheWaitSwitch,
+        DcacheRetry,
+        DcacheWaitResponse,
+        DcacheWaitSwitch,
+        SwitchedOut
+    };
+
+    Status _status;
+
+  public:
 
 #if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
@@ -131,9 +151,6 @@ class BaseSimpleCPU : public BaseCPU
     // The predecoder
     TheISA::Predecoder predecoder;
 
-    // Static data storage
-    TheISA::LargestRead dataReg;
-
     StaticInstPtr curStaticInst;
     StaticInstPtr curMacroStaticInst;
 
@@ -161,11 +178,22 @@ class BaseSimpleCPU : public BaseCPU
     Counter startNumInst;
     Stats::Scalar<> numInsts;
 
+    void countInst()
+    {
+        numInst++;
+        numInsts++;
+
+        thread->funcExeInst++;
+    }
+
     virtual Counter totalInstructions() const
     {
         return numInst - startNumInst;
     }
 
+    // Mask to align PCs to MachInst sized boundaries
+    static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
+
     // number of simulated memory references
     Stats::Scalar<> numMemRefs;
 
@@ -212,6 +240,7 @@ class BaseSimpleCPU : public BaseCPU
         // need to do this...
     }
 
+
     Fault copySrcTranslate(Addr src);
 
     Fault copy(Addr dest);
@@ -290,11 +319,15 @@ class BaseSimpleCPU : public BaseCPU
     }
 
     uint64_t readPC() { return thread->readPC(); }
+    uint64_t readMicroPC() { return thread->readMicroPC(); }
     uint64_t readNextPC() { return thread->readNextPC(); }
+    uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
     uint64_t readNextNPC() { return thread->readNextNPC(); }
 
     void setPC(uint64_t val) { thread->setPC(val); }
+    void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
     void setNextPC(uint64_t val) { thread->setNextPC(val); }
+    void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
     void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
 
     MiscReg readMiscRegNoEffect(int misc_reg)
@@ -342,6 +375,21 @@ class BaseSimpleCPU : public BaseCPU
         return thread->setMiscReg(reg_idx, val);
     }
 
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        thread->demapPage(vaddr, asn);
+    }
+
+    void demapInstPage(Addr vaddr, uint64_t asn)
+    {
+        thread->demapInstPage(vaddr, asn);
+    }
+
+    void demapDataPage(Addr vaddr, uint64_t asn)
+    {
+        thread->demapDataPage(vaddr, asn);
+    }
+
     unsigned readStCondFailures() {
         return thread->readStCondFailures();
     }
@@ -350,6 +398,20 @@ class BaseSimpleCPU : public BaseCPU
         thread->setStCondFailures(sc_failures);
     }
 
+     MiscReg readRegOtherThread(int regIdx, int tid = -1)
+     {
+        panic("Simple CPU models do not support multithreaded "
+              "register access.\n");
+     }
+
+     void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
+     {
+        panic("Simple CPU models do not support multithreaded "
+              "register access.\n");
+     }
+
+    //Fault CacheOp(uint8_t Op, Addr EA);
+
 #if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }