#ifndef __CPU_SIMPLE_BASE_HH__
#define __CPU_SIMPLE_BASE_HH__
+#include "arch/predecoder.hh"
#include "base/statistics.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
+#include "sim/system.hh"
// forward declarations
#if FULL_SYSTEM
class RemoteGDB;
class GDBListener;
+namespace TheISA
+{
+ class Predecoder;
+}
class ThreadContext;
class Checkpoint;
class InstRecord;
}
+class BaseSimpleCPUParams;
+
class BaseSimpleCPU : public BaseCPU
{
protected:
- typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
protected:
Trace::InstRecord *traceData;
+ inline void checkPcEventQueue() {
+ Addr oldpc;
+ do {
+ oldpc = thread->readPC();
+ system->pcEventQueue.service(tc);
+ } while (oldpc != thread->readPC());
+ }
+
public:
- void post_interrupt(int int_num, int index);
+ void wakeup();
void zero_fill_64(Addr addr) {
static int warned = 0;
};
public:
- struct Params : public BaseCPU::Params
- {
-#if FULL_SYSTEM
- TheISA::ITB *itb;
- TheISA::DTB *dtb;
-#else
- Process *process;
-#endif
- };
- BaseSimpleCPU(Params *params);
+ BaseSimpleCPU(BaseSimpleCPUParams *params);
virtual ~BaseSimpleCPU();
public:
* objects to modify this thread's state.
*/
ThreadContext *tc;
+ protected:
+
+ enum Status {
+ Idle,
+ Running,
+ ITBWaitResponse,
+ IcacheRetry,
+ IcacheWaitResponse,
+ IcacheWaitSwitch,
+ DTBWaitResponse,
+ DcacheRetry,
+ DcacheWaitResponse,
+ DcacheWaitSwitch,
+ SwitchedOut
+ };
+
+ Status _status;
+
+ public:
#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
#endif
// current instruction
- MachInst inst;
+ TheISA::MachInst inst;
- // Static data storage
- TheISA::IntReg dataReg;
+ // The predecoder
+ TheISA::Predecoder predecoder;
StaticInstPtr curStaticInst;
StaticInstPtr curMacroStaticInst;
+ //This is the offset from the current pc that fetch should be performed at
+ Addr fetchOffset;
+ //This flag says to stay at the current pc. This is useful for
+ //instructions which go beyond MachInst boundaries.
+ bool stayAtPC;
+
void checkForInterrupts();
- Fault setupFetchRequest(Request *req);
+ void setupFetchRequest(Request *req);
void preExecute();
void postExecute();
void advancePC(Fault fault);
// number of simulated instructions
Counter numInst;
Counter startNumInst;
- Stats::Scalar<> numInsts;
+ Stats::Scalar numInsts;
+
+ void countInst()
+ {
+ numInst++;
+ numInsts++;
+
+ thread->funcExeInst++;
+ }
virtual Counter totalInstructions() const
{
return numInst - startNumInst;
}
+ // Mask to align PCs to MachInst sized boundaries
+ static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
+
// number of simulated memory references
- Stats::Scalar<> numMemRefs;
+ Stats::Scalar numMemRefs;
// number of simulated loads
Counter numLoad;
Counter startNumLoad;
// number of idle cycles
- Stats::Average<> notIdleFraction;
+ Stats::Average notIdleFraction;
Stats::Formula idleFraction;
// number of cycles stalled for I-cache responses
- Stats::Scalar<> icacheStallCycles;
+ Stats::Scalar icacheStallCycles;
Counter lastIcacheStall;
// number of cycles stalled for I-cache retries
- Stats::Scalar<> icacheRetryCycles;
+ Stats::Scalar icacheRetryCycles;
Counter lastIcacheRetry;
// number of cycles stalled for D-cache responses
- Stats::Scalar<> dcacheStallCycles;
+ Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
// number of cycles stalled for D-cache retries
- Stats::Scalar<> dcacheRetryCycles;
+ Stats::Scalar dcacheRetryCycles;
Counter lastDcacheRetry;
virtual void serialize(std::ostream &os);
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
- Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
+ Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
M5_DUMMY_RETURN}
void prefetch(Addr addr, unsigned flags)
// need to do this...
}
+
Fault copySrcTranslate(Addr src);
Fault copy(Addr dest);
}
uint64_t readPC() { return thread->readPC(); }
+ uint64_t readMicroPC() { return thread->readMicroPC(); }
uint64_t readNextPC() { return thread->readNextPC(); }
+ uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
uint64_t readNextNPC() { return thread->readNextNPC(); }
void setPC(uint64_t val) { thread->setPC(val); }
+ void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
void setNextPC(uint64_t val) { thread->setNextPC(val); }
+ void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
+ MiscReg readMiscRegNoEffect(int misc_reg)
+ {
+ return thread->readMiscRegNoEffect(misc_reg);
+ }
+
MiscReg readMiscReg(int misc_reg)
{
return thread->readMiscReg(misc_reg);
}
- MiscReg readMiscRegWithEffect(int misc_reg)
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
- return thread->readMiscRegWithEffect(misc_reg);
+ return thread->setMiscRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val)
return thread->setMiscReg(misc_reg, val);
}
- void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
- return thread->setMiscRegWithEffect(misc_reg, val);
+ int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ return thread->readMiscRegNoEffect(reg_idx);
}
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
return thread->readMiscReg(reg_idx);
}
- MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
+ void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
{
- int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return thread->readMiscRegWithEffect(reg_idx);
+ int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ return thread->setMiscRegNoEffect(reg_idx, val);
}
- void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
+ void setMiscRegOperand(
+ const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscReg(reg_idx, val);
}
- void setMiscRegOperandWithEffect(
- const StaticInst *si, int idx, const MiscReg &val)
+ void demapPage(Addr vaddr, uint64_t asn)
{
- int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return thread->setMiscRegWithEffect(reg_idx, val);
+ thread->demapPage(vaddr, asn);
}
+ void demapInstPage(Addr vaddr, uint64_t asn)
+ {
+ thread->demapInstPage(vaddr, asn);
+ }
+
+ void demapDataPage(Addr vaddr, uint64_t asn)
+ {
+ thread->demapDataPage(vaddr, asn);
+ }
+
+ unsigned readStCondFailures() {
+ return thread->readStCondFailures();
+ }
+
+ void setStCondFailures(unsigned sc_failures) {
+ thread->setStCondFailures(sc_failures);
+ }
+
+ MiscReg readRegOtherThread(int regIdx, int tid = -1)
+ {
+ panic("Simple CPU models do not support multithreaded "
+ "register access.\n");
+ }
+
+ void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
+ {
+ panic("Simple CPU models do not support multithreaded "
+ "register access.\n");
+ }
+
+ //Fault CacheOp(uint8_t Op, Addr EA);
+
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
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