inorder/alpha-isa: create eaComp object visible to StaticInst through ISA

[gem5.git] / src / cpu / simple / timing.cc

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a8f86f8d270d5b5846c550033b67113d9d5d24eb..590ba6b2d8db6d35ab50438519adf8ebfa0b8e38 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -233,6 +233,9 @@ TimingSimpleCPU::suspendContext(int thread_num)
     assert(thread_num == 0);
     assert(thread);
 
+    if (_status == Idle)
+        return;
+
     assert(_status == Running);
 
     // just change status to Idle... if status != Running,
@@ -287,7 +290,7 @@ TimingSimpleCPU::sendData(Fault fault, RequestPtr req,
     } else {
         bool do_access = true;  // flag to suppress cache access
 
-        if (req->isLocked()) {
+        if (req->isLLSC()) {
             do_access = TheISA::handleLockedWrite(thread, req);
         } else if (req->isCondSwap()) {
             assert(res);
@@ -381,11 +384,11 @@ TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
     MemCmd cmd;
     if (read) {
         cmd = MemCmd::ReadReq;
-        if (req->isLocked())
+        if (req->isLLSC())
             cmd = MemCmd::LoadLockedReq;
     } else {
         cmd = MemCmd::WriteReq;
-        if (req->isLocked()) {
+        if (req->isLLSC()) {
             cmd = MemCmd::StoreCondReq;
         } else if (req->isSwap()) {
             cmd = MemCmd::SwapReq;
@@ -449,20 +452,20 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
     _status = DTBWaitResponse;
     if (split_addr > addr) {
         RequestPtr req1, req2;
-        assert(!req->isLocked() && !req->isSwap());
+        assert(!req->isLLSC() && !req->isSwap());
         req->splitOnVaddr(split_addr, req1, req2);
 
         typedef SplitDataTranslation::WholeTranslationState WholeState;
         WholeState *state = new WholeState(req1, req2, req,
-                (uint8_t *)(new T), true);
+                                           (uint8_t *)(new T), BaseTLB::Read);
         thread->dtb->translateTiming(req1, tc,
-                new SplitDataTranslation(this, 0, state), false);
+                new SplitDataTranslation(this, 0, state), BaseTLB::Read);
         thread->dtb->translateTiming(req2, tc,
-                new SplitDataTranslation(this, 1, state), false);
+                new SplitDataTranslation(this, 1, state), BaseTLB::Read);
     } else {
-        thread->dtb->translateTiming(req, tc,
-                new DataTranslation(this, (uint8_t *)(new T), NULL, true),
-                false);
+        DataTranslation *translation =
+            new DataTranslation(this, (uint8_t *)(new T), NULL, BaseTLB::Read);
+        thread->dtb->translateTiming(req, tc, translation, BaseTLB::Read);
     }
 
     if (traceData) {
@@ -568,20 +571,20 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     _status = DTBWaitResponse;
     if (split_addr > addr) {
         RequestPtr req1, req2;
-        assert(!req->isLocked() && !req->isSwap());
+        assert(!req->isLLSC() && !req->isSwap());
         req->splitOnVaddr(split_addr, req1, req2);
 
         typedef SplitDataTranslation::WholeTranslationState WholeState;
         WholeState *state = new WholeState(req1, req2, req,
-                (uint8_t *)dataP, false);
+                (uint8_t *)dataP, BaseTLB::Write);
         thread->dtb->translateTiming(req1, tc,
-                new SplitDataTranslation(this, 0, state), true);
+                new SplitDataTranslation(this, 0, state), BaseTLB::Write);
         thread->dtb->translateTiming(req2, tc,
-                new SplitDataTranslation(this, 1, state), true);
+                new SplitDataTranslation(this, 1, state), BaseTLB::Write);
     } else {
-        thread->dtb->translateTiming(req, tc,
-                new DataTranslation(this, (uint8_t *)dataP, res, false),
-                true);
+        DataTranslation *translation =
+            new DataTranslation(this, (uint8_t *)dataP, res, BaseTLB::Write);
+        thread->dtb->translateTiming(req, tc, translation, BaseTLB::Write);
     }
 
     if (traceData) {
@@ -671,8 +674,8 @@ TimingSimpleCPU::fetch()
         Request *ifetch_req = new Request();
         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         setupFetchRequest(ifetch_req);
-        thread->itb->translateTiming(ifetch_req, tc,
-                &fetchTranslation);
+        thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
+                BaseTLB::Execute);
     } else {
         _status = IcacheWaitResponse;
         completeIfetch(NULL);
@@ -901,7 +904,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
 
     // the locked flag may be cleared on the response packet, so check
     // pkt->req and not pkt to see if it was a load-locked
-    if (pkt->isRead() && pkt->req->isLocked()) {
+    if (pkt->isRead() && pkt->req->isLLSC()) {
         TheISA::handleLockedRead(thread, pkt->req);
     }