/*
+ * Copyright 2014 Google, Inc.
+ * Copyright (c) 2010-2013,2015,2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Authors: Steve Reinhardt
*/
+#include "cpu/simple/timing.hh"
+
#include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
-#include "cpu/simple/timing.hh"
+#include "debug/Config.hh"
+#include "debug/Drain.hh"
+#include "debug/ExecFaulting.hh"
+#include "debug/Mwait.hh"
+#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/TimingSimpleCPU.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
-Port *
-TimingSimpleCPU::getPort(const std::string &if_name, int idx)
-{
- if (if_name == "dcache_port")
- return &dcachePort;
- else if (if_name == "icache_port")
- return &icachePort;
- else
- panic("No Such Port\n");
-}
-
void
TimingSimpleCPU::init()
{
- BaseCPU::init();
-#if FULL_SYSTEM
- for (int i = 0; i < threadContexts.size(); ++i) {
- ThreadContext *tc = threadContexts[i];
-
- // initialize CPU, including PC
- TheISA::initCPU(tc, _cpuId);
- }
-#endif
-}
-
-Tick
-TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
-{
- panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
- return curTick;
+ BaseSimpleCPU::init();
}
void
-TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
-{
- //No internal storage to update, jusst return
- return;
-}
-
-void
-TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
-{
- if (status == RangeChange) {
- if (!snoopRangeSent) {
- snoopRangeSent = true;
- sendStatusChange(Port::RangeChange);
- }
- return;
- }
-
- panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
-}
-
-
-void
-TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
+TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
{
pkt = _pkt;
cpu->schedule(this, t);
}
TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
- : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock),
- dcachePort(this, p->clock), fetchEvent(this)
+ : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
+ dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
+ fetchEvent([this]{ fetch(); }, name())
{
_status = Idle;
-
- icachePort.snoopRangeSent = false;
- dcachePort.snoopRangeSent = false;
-
- ifetch_pkt = dcache_pkt = NULL;
- drainEvent = NULL;
- previousTick = 0;
- changeState(SimObject::Running);
}
+
TimingSimpleCPU::~TimingSimpleCPU()
{
}
-void
-TimingSimpleCPU::serialize(ostream &os)
+DrainState
+TimingSimpleCPU::drain()
{
- SimObject::State so_state = SimObject::getState();
- SERIALIZE_ENUM(so_state);
- BaseSimpleCPU::serialize(os);
-}
+ // Deschedule any power gating event (if any)
+ deschedulePowerGatingEvent();
-void
-TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
-{
- SimObject::State so_state;
- UNSERIALIZE_ENUM(so_state);
- BaseSimpleCPU::unserialize(cp, section);
-}
+ if (switchedOut())
+ return DrainState::Drained;
-unsigned int
-TimingSimpleCPU::drain(Event *drain_event)
-{
- // TimingSimpleCPU is ready to drain if it's not waiting for
- // an access to complete.
- if (_status == Idle || _status == Running || _status == SwitchedOut) {
- changeState(SimObject::Drained);
- return 0;
+ if (_status == Idle ||
+ (_status == BaseSimpleCPU::Running && isDrained())) {
+ DPRINTF(Drain, "No need to drain.\n");
+ activeThreads.clear();
+ return DrainState::Drained;
} else {
- changeState(SimObject::Draining);
- drainEvent = drain_event;
- return 1;
+ DPRINTF(Drain, "Requesting drain.\n");
+
+ // The fetch event can become descheduled if a drain didn't
+ // succeed on the first attempt. We need to reschedule it if
+ // the CPU is waiting for a microcode routine to complete.
+ if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled())
+ schedule(fetchEvent, clockEdge());
+
+ return DrainState::Draining;
}
}
void
-TimingSimpleCPU::resume()
+TimingSimpleCPU::drainResume()
{
+ assert(!fetchEvent.scheduled());
+ if (switchedOut())
+ return;
+
DPRINTF(SimpleCPU, "Resume\n");
- if (_status != SwitchedOut && _status != Idle) {
- assert(system->getMemoryMode() == Enums::timing);
+ verifyMemoryMode();
- if (fetchEvent.scheduled())
- deschedule(fetchEvent);
+ assert(!threadContexts.empty());
- schedule(fetchEvent, nextCycle());
+ _status = BaseSimpleCPU::Idle;
+
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
+ if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
+ threadInfo[tid]->notIdleFraction = 1;
+
+ activeThreads.push_back(tid);
+
+ _status = BaseSimpleCPU::Running;
+
+ // Fetch if any threads active
+ if (!fetchEvent.scheduled()) {
+ schedule(fetchEvent, nextCycle());
+ }
+ } else {
+ threadInfo[tid]->notIdleFraction = 0;
+ }
}
- changeState(SimObject::Running);
+ // Reschedule any power gating event (if any)
+ schedulePowerGatingEvent();
+
+ system->totalNumInsts = 0;
+}
+
+bool
+TimingSimpleCPU::tryCompleteDrain()
+{
+ if (drainState() != DrainState::Draining)
+ return false;
+
+ DPRINTF(Drain, "tryCompleteDrain.\n");
+ if (!isDrained())
+ return false;
+
+ DPRINTF(Drain, "CPU done draining, processing drain event\n");
+ signalDrainDone();
+
+ return true;
}
void
TimingSimpleCPU::switchOut()
{
- assert(_status == Running || _status == Idle);
- _status = SwitchedOut;
- numCycles += tickToCycles(curTick - previousTick);
-
- // If we've been scheduled to resume but are then told to switch out,
- // we'll need to cancel it.
- if (fetchEvent.scheduled())
- deschedule(fetchEvent);
+ SimpleExecContext& t_info = *threadInfo[curThread];
+ M5_VAR_USED SimpleThread* thread = t_info.thread;
+
+ BaseSimpleCPU::switchOut();
+
+ assert(!fetchEvent.scheduled());
+ assert(_status == BaseSimpleCPU::Running || _status == Idle);
+ assert(!t_info.stayAtPC);
+ assert(thread->microPC() == 0);
+
+ updateCycleCounts();
}
void
TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
{
- BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
-
- // if any of this CPU's ThreadContexts are active, mark the CPU as
- // running and schedule its tick event.
- for (int i = 0; i < threadContexts.size(); ++i) {
- ThreadContext *tc = threadContexts[i];
- if (tc->status() == ThreadContext::Active && _status != Running) {
- _status = Running;
- break;
- }
- }
+ BaseSimpleCPU::takeOverFrom(oldCPU);
- if (_status != Running) {
- _status = Idle;
- }
- assert(threadContexts.size() == 1);
- previousTick = curTick;
+ previousCycle = curCycle();
}
-
void
-TimingSimpleCPU::activateContext(int thread_num, int delay)
+TimingSimpleCPU::verifyMemoryMode() const
{
- DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
+ if (!system->isTimingMode()) {
+ fatal("The timing CPU requires the memory system to be in "
+ "'timing' mode.\n");
+ }
+}
- assert(thread_num == 0);
- assert(thread);
+void
+TimingSimpleCPU::activateContext(ThreadID thread_num)
+{
+ DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
- assert(_status == Idle);
+ assert(thread_num < numThreads);
- notIdleFraction++;
- _status = Running;
+ threadInfo[thread_num]->notIdleFraction = 1;
+ if (_status == BaseSimpleCPU::Idle)
+ _status = BaseSimpleCPU::Running;
// kick things off by initiating the fetch of the next instruction
- schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
+ if (!fetchEvent.scheduled())
+ schedule(fetchEvent, clockEdge(Cycles(0)));
+
+ if (std::find(activeThreads.begin(), activeThreads.end(), thread_num)
+ == activeThreads.end()) {
+ activeThreads.push_back(thread_num);
+ }
+
+ BaseCPU::activateContext(thread_num);
}
void
-TimingSimpleCPU::suspendContext(int thread_num)
+TimingSimpleCPU::suspendContext(ThreadID thread_num)
{
DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
- assert(thread_num == 0);
- assert(thread);
+ assert(thread_num < numThreads);
+ activeThreads.remove(thread_num);
if (_status == Idle)
return;
- assert(_status == Running);
+ assert(_status == BaseSimpleCPU::Running);
- // just change status to Idle... if status != Running,
- // completeInst() will not initiate fetch of next instruction.
+ threadInfo[thread_num]->notIdleFraction = 0;
- notIdleFraction--;
- _status = Idle;
+ if (activeThreads.empty()) {
+ _status = Idle;
+
+ if (fetchEvent.scheduled()) {
+ deschedule(fetchEvent);
+ }
+ }
+
+ BaseCPU::suspendContext(thread_num);
}
bool
TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
{
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
RequestPtr req = pkt->req;
- if (req->isMmapedIpr()) {
- Tick delay;
- delay = TheISA::handleIprRead(thread->getTC(), pkt);
- new IprEvent(pkt, this, nextCycle(curTick + delay));
+
+ // We're about the issues a locked load, so tell the monitor
+ // to start caring about this address
+ if (pkt->isRead() && pkt->req->isLLSC()) {
+ TheISA::handleLockedRead(thread, pkt->req);
+ }
+ if (req->isMmappedIpr()) {
+ Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
+ new IprEvent(pkt, this, clockEdge(delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
- } else if (!dcachePort.sendTiming(pkt)) {
+ } else if (!dcachePort.sendTimingReq(pkt)) {
_status = DcacheRetry;
dcache_pkt = pkt;
} else {
TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
bool read)
{
- PacketPtr pkt;
- buildPacket(pkt, req, read);
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
+ PacketPtr pkt = buildPacket(req, read);
pkt->dataDynamic<uint8_t>(data);
if (req->getFlags().isSet(Request::NO_ACCESS)) {
assert(!dcache_pkt);
bool do_access = true; // flag to suppress cache access
if (req->isLLSC()) {
- do_access = TheISA::handleLockedWrite(thread, req);
+ do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
} else if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
if (do_access) {
dcache_pkt = pkt;
handleWritePacket();
+ threadSnoop(pkt, curThread);
} else {
_status = DcacheWaitResponse;
completeDataAccess(pkt);
pkt1->makeResponse();
completeDataAccess(pkt1);
} else if (read) {
+ SplitFragmentSenderState * send_state =
+ dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
if (handleReadPacket(pkt1)) {
- SplitFragmentSenderState * send_state =
- dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
send_state->clearFromParent();
+ send_state = dynamic_cast<SplitFragmentSenderState *>(
+ pkt2->senderState);
if (handleReadPacket(pkt2)) {
- send_state = dynamic_cast<SplitFragmentSenderState *>(
- pkt1->senderState);
send_state->clearFromParent();
}
}
} else {
dcache_pkt = pkt1;
+ SplitFragmentSenderState * send_state =
+ dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
if (handleWritePacket()) {
- SplitFragmentSenderState * send_state =
- dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
send_state->clearFromParent();
dcache_pkt = pkt2;
+ send_state = dynamic_cast<SplitFragmentSenderState *>(
+ pkt2->senderState);
if (handleWritePacket()) {
- send_state = dynamic_cast<SplitFragmentSenderState *>(
- pkt1->senderState);
send_state->clearFromParent();
}
}
}
void
-TimingSimpleCPU::translationFault(Fault fault)
+TimingSimpleCPU::translationFault(const Fault &fault)
{
// fault may be NoFault in cases where a fault is suppressed,
// for instance prefetches.
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ updateCycleCounts();
if (traceData) {
// Since there was a fault, we shouldn't trace this instruction.
postExecute();
- if (getState() == SimObject::Draining) {
- advancePC(fault);
- completeDrain();
- } else {
- advanceInst(fault);
- }
+ advanceInst(fault);
}
-void
-TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
+PacketPtr
+TimingSimpleCPU::buildPacket(RequestPtr req, bool read)
{
- MemCmd cmd;
- if (read) {
- cmd = MemCmd::ReadReq;
- if (req->isLLSC())
- cmd = MemCmd::LoadLockedReq;
- } else {
- cmd = MemCmd::WriteReq;
- if (req->isLLSC()) {
- cmd = MemCmd::StoreCondReq;
- } else if (req->isSwap()) {
- cmd = MemCmd::SwapReq;
- }
- }
- pkt = new Packet(req, cmd, Packet::Broadcast);
+ return read ? Packet::createRead(req) : Packet::createWrite(req);
}
void
{
pkt1 = pkt2 = NULL;
- assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
+ assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
if (req->getFlags().isSet(Request::NO_ACCESS)) {
- buildPacket(pkt1, req, read);
+ pkt1 = buildPacket(req, read);
return;
}
- buildPacket(pkt1, req1, read);
- buildPacket(pkt2, req2, read);
+ pkt1 = buildPacket(req1, read);
+ pkt2 = buildPacket(req2, read);
- req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
- PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
- Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
pkt->dataDynamic<uint8_t>(data);
pkt1->dataStatic<uint8_t>(data);
}
Fault
-TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
- unsigned size, unsigned flags)
+TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
+ unsigned size, Request::Flags flags)
+{
+ panic("readMem() is for atomic accesses, and should "
+ "never be called on TimingSimpleCPU.\n");
+}
+
+Fault
+TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
+ Request::Flags flags)
{
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
Fault fault;
const int asid = 0;
- const ThreadID tid = 0;
- const Addr pc = thread->readPC();
- unsigned block_size = dcachePort.peerBlockSize();
+ const Addr pc = thread->instAddr();
+ unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Read;
- if (traceData) {
- traceData->setAddr(addr);
- }
+ if (traceData)
+ traceData->setMem(addr, size, flags);
- RequestPtr req = new Request(asid, addr, size,
- flags, pc, _cpuId, tid);
+ RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
+ thread->contextId());
+
+ req->taskId(taskId());
Addr split_addr = roundDown(addr + size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
WholeTranslationState *state =
new WholeTranslationState(req, req1, req2, new uint8_t[size],
NULL, mode);
- DataTranslation<TimingSimpleCPU> *trans1 =
- new DataTranslation<TimingSimpleCPU>(this, state, 0);
- DataTranslation<TimingSimpleCPU> *trans2 =
- new DataTranslation<TimingSimpleCPU>(this, state, 1);
+ DataTranslation<TimingSimpleCPU *> *trans1 =
+ new DataTranslation<TimingSimpleCPU *>(this, state, 0);
+ DataTranslation<TimingSimpleCPU *> *trans2 =
+ new DataTranslation<TimingSimpleCPU *>(this, state, 1);
- thread->dtb->translateTiming(req1, tc, trans1, mode);
- thread->dtb->translateTiming(req2, tc, trans2, mode);
+ thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
+ thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
} else {
WholeTranslationState *state =
new WholeTranslationState(req, new uint8_t[size], NULL, mode);
- DataTranslation<TimingSimpleCPU> *translation
- = new DataTranslation<TimingSimpleCPU>(this, state);
- thread->dtb->translateTiming(req, tc, translation, mode);
+ DataTranslation<TimingSimpleCPU *> *translation
+ = new DataTranslation<TimingSimpleCPU *>(this, state);
+ thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
}
return NoFault;
}
-template <class T>
-Fault
-TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
-{
- return readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
-{
- return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
-{
- return read(addr, *(uint32_t*)&data, flags);
-}
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
-{
- return read(addr, (uint32_t&)data, flags);
-}
-
bool
TimingSimpleCPU::handleWritePacket()
{
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
RequestPtr req = dcache_pkt->req;
- if (req->isMmapedIpr()) {
- Tick delay;
- delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
- new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
+ if (req->isMmappedIpr()) {
+ Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
+ new IprEvent(dcache_pkt, this, clockEdge(delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
- } else if (!dcachePort.sendTiming(dcache_pkt)) {
+ } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
_status = DcacheRetry;
} else {
_status = DcacheWaitResponse;
}
Fault
-TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
+ Addr addr, Request::Flags flags, uint64_t *res)
{
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
+ uint8_t *newData = new uint8_t[size];
const int asid = 0;
- const ThreadID tid = 0;
- const Addr pc = thread->readPC();
- unsigned block_size = dcachePort.peerBlockSize();
+ const Addr pc = thread->instAddr();
+ unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Write;
- if (traceData) {
- traceData->setAddr(addr);
+ if (data == NULL) {
+ assert(flags & Request::CACHE_BLOCK_ZERO);
+ // This must be a cache block cleaning request
+ memset(newData, 0, size);
+ } else {
+ memcpy(newData, data, size);
}
- RequestPtr req = new Request(asid, addr, size,
- flags, pc, _cpuId, tid);
+ if (traceData)
+ traceData->setMem(addr, size, flags);
+
+ RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
+ thread->contextId());
+
+ req->taskId(taskId());
Addr split_addr = roundDown(addr + size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
req->splitOnVaddr(split_addr, req1, req2);
WholeTranslationState *state =
- new WholeTranslationState(req, req1, req2, data, res, mode);
- DataTranslation<TimingSimpleCPU> *trans1 =
- new DataTranslation<TimingSimpleCPU>(this, state, 0);
- DataTranslation<TimingSimpleCPU> *trans2 =
- new DataTranslation<TimingSimpleCPU>(this, state, 1);
-
- thread->dtb->translateTiming(req1, tc, trans1, mode);
- thread->dtb->translateTiming(req2, tc, trans2, mode);
+ new WholeTranslationState(req, req1, req2, newData, res, mode);
+ DataTranslation<TimingSimpleCPU *> *trans1 =
+ new DataTranslation<TimingSimpleCPU *>(this, state, 0);
+ DataTranslation<TimingSimpleCPU *> *trans2 =
+ new DataTranslation<TimingSimpleCPU *>(this, state, 1);
+
+ thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
+ thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
} else {
WholeTranslationState *state =
- new WholeTranslationState(req, data, res, mode);
- DataTranslation<TimingSimpleCPU> *translation =
- new DataTranslation<TimingSimpleCPU>(this, state);
- thread->dtb->translateTiming(req, tc, translation, mode);
+ new WholeTranslationState(req, newData, res, mode);
+ DataTranslation<TimingSimpleCPU *> *translation =
+ new DataTranslation<TimingSimpleCPU *>(this, state);
+ thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
}
// Translation faults will be returned via finishTranslation()
return NoFault;
}
-Fault
-TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
-{
- uint8_t *newData = new uint8_t[size];
- memcpy(newData, data, size);
- return writeTheseBytes(newData, size, addr, flags, res);
-}
-
-template <class T>
-Fault
-TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+void
+TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
{
- if (traceData) {
- traceData->setData(data);
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
+ if (tid != sender) {
+ if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
+ wakeup(tid);
+ }
+ TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
+ dcachePort.cacheBlockMask);
+ }
}
- T *dataP = new T;
- *dataP = TheISA::htog(data);
-
- return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res);
-}
-
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template
-Fault
-TimingSimpleCPU::write(Twin32_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(Twin64_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint64_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint32_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint16_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint8_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint32_t*)&data, addr, flags, res);
}
-
-template<>
-Fault
-TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write((uint32_t)data, addr, flags, res);
-}
-
-
void
TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
{
- _status = Running;
+ _status = BaseSimpleCPU::Running;
if (state->getFault() != NoFault) {
if (state->isPrefetch()) {
state->setNoFault();
}
- delete state->data;
+ delete [] state->data;
state->deleteReqs();
translationFault(state->getFault());
} else {
void
TimingSimpleCPU::fetch()
{
+ // Change thread if multi-threaded
+ swapActiveThread();
+
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ SimpleThread* thread = t_info.thread;
+
DPRINTF(SimpleCPU, "Fetch\n");
- if (!curStaticInst || !curStaticInst->isDelayedCommit())
+ if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
checkForInterrupts();
+ checkPcEventQueue();
+ }
- checkPcEventQueue();
+ // We must have just got suspended by a PC event
+ if (_status == Idle)
+ return;
- bool fromRom = isRomMicroPC(thread->readMicroPC());
+ TheISA::PCState pcState = thread->pcState();
+ bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
+ !curMacroStaticInst;
- if (!fromRom && !curMacroStaticInst) {
+ if (needToFetch) {
+ _status = BaseSimpleCPU::Running;
Request *ifetch_req = new Request();
- ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
+ ifetch_req->taskId(taskId());
+ ifetch_req->setContext(thread->contextId());
setupFetchRequest(ifetch_req);
- thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
- BaseTLB::Execute);
+ DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
+ thread->itb->translateTiming(ifetch_req, thread->getTC(),
+ &fetchTranslation, BaseTLB::Execute);
} else {
_status = IcacheWaitResponse;
completeIfetch(NULL);
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ updateCycleCounts();
}
}
void
-TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
+TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
+ ThreadContext *tc)
{
if (fault == NoFault) {
- ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
+ req->getVaddr(), req->getPaddr());
+ ifetch_pkt = new Packet(req, MemCmd::ReadReq);
ifetch_pkt->dataStatic(&inst);
+ DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
- if (!icachePort.sendTiming(ifetch_pkt)) {
+ if (!icachePort.sendTimingReq(ifetch_pkt)) {
// Need to wait for retry
_status = IcacheRetry;
} else {
ifetch_pkt = NULL;
}
} else {
+ DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
delete req;
// fetch fault: advance directly to next instruction (fault handler)
+ _status = BaseSimpleCPU::Running;
advanceInst(fault);
}
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ updateCycleCounts();
}
void
-TimingSimpleCPU::advanceInst(Fault fault)
+TimingSimpleCPU::advanceInst(const Fault &fault)
{
- if (fault != NoFault || !stayAtPC)
+ SimpleExecContext &t_info = *threadInfo[curThread];
+
+ if (_status == Faulting)
+ return;
+
+ if (fault != NoFault) {
+ DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
+
advancePC(fault);
- if (_status == Running) {
+ Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ?
+ clockEdge(syscallRetryLatency) : clockEdge();
+
+ reschedule(fetchEvent, stall, true);
+
+ _status = Faulting;
+ return;
+ }
+
+
+ if (!t_info.stayAtPC)
+ advancePC(fault);
+
+ if (tryCompleteDrain())
+ return;
+
+ if (_status == BaseSimpleCPU::Running) {
// kick off fetch of next instruction... callback from icache
// response will cause that instruction to be executed,
// keeping the CPU running.
void
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
- DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
+ SimpleExecContext& t_info = *threadInfo[curThread];
+
+ DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
+ pkt->getAddr() : 0);
// received a response from the icache: execute the received
// instruction
-
assert(!pkt || !pkt->isError());
assert(_status == IcacheWaitResponse);
- _status = Running;
+ _status = BaseSimpleCPU::Running;
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ updateCycleCounts();
- if (getState() == SimObject::Draining) {
- if (pkt) {
- delete pkt->req;
- delete pkt;
- }
+ if (pkt)
+ pkt->req->setAccessLatency();
- completeDrain();
- return;
- }
preExecute();
- if (curStaticInst &&
- curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
+ if (curStaticInst && curStaticInst->isMemRef()) {
// load or store: just send to dcache
- Fault fault = curStaticInst->initiateAcc(this, traceData);
- if (_status != Running) {
- // instruction will complete in dcache response callback
- assert(_status == DcacheWaitResponse ||
- _status == DcacheRetry || DTBWaitResponse);
- assert(fault == NoFault);
- } else {
+ Fault fault = curStaticInst->initiateAcc(&t_info, traceData);
+
+ // If we're not running now the instruction will complete in a dcache
+ // response callback or the instruction faulted and has started an
+ // ifetch
+ if (_status == BaseSimpleCPU::Running) {
if (fault != NoFault && traceData) {
// If there was a fault, we shouldn't trace this instruction.
delete traceData;
}
} else if (curStaticInst) {
// non-memory instruction: execute completely now
- Fault fault = curStaticInst->execute(this, traceData);
+ Fault fault = curStaticInst->execute(&t_info, traceData);
// keep an instruction count
if (fault == NoFault)
postExecute();
// @todo remove me after debugging with legion done
if (curStaticInst && (!curStaticInst->isMicroop() ||
- curStaticInst->isFirstMicroop()))
+ curStaticInst->isFirstMicroop()))
instCnt++;
advanceInst(fault);
} else {
}
bool
-TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
+TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
{
- if (pkt->isResponse() && !pkt->wasNacked()) {
- // delay processing of returned data until next CPU clock edge
- Tick next_tick = cpu->nextCycle(curTick);
+ DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr());
+ // we should only ever see one response per cycle since we only
+ // issue a new request once this response is sunk
+ assert(!tickEvent.scheduled());
+ // delay processing of returned data until next CPU clock edge
+ tickEvent.schedule(pkt, cpu->clockEdge());
- if (next_tick == curTick)
- cpu->completeIfetch(pkt);
- else
- tickEvent.schedule(pkt, next_tick);
-
- return true;
- }
- else if (pkt->wasNacked()) {
- assert(cpu->_status == IcacheWaitResponse);
- pkt->reinitNacked();
- if (!sendTiming(pkt)) {
- cpu->_status = IcacheRetry;
- cpu->ifetch_pkt = pkt;
- }
- }
- //Snooping a Coherence Request, do nothing
return true;
}
void
-TimingSimpleCPU::IcachePort::recvRetry()
+TimingSimpleCPU::IcachePort::recvReqRetry()
{
// we shouldn't get a retry unless we have a packet that we're
// waiting to transmit
assert(cpu->ifetch_pkt != NULL);
assert(cpu->_status == IcacheRetry);
PacketPtr tmp = cpu->ifetch_pkt;
- if (sendTiming(tmp)) {
+ if (sendTimingReq(tmp)) {
cpu->_status = IcacheWaitResponse;
cpu->ifetch_pkt = NULL;
}
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
pkt->req->getFlags().isSet(Request::NO_ACCESS));
- numCycles += tickToCycles(curTick - previousTick);
- previousTick = curTick;
+ pkt->req->setAccessLatency();
+
+ updateCycleCounts();
if (pkt->senderState) {
SplitFragmentSenderState * send_state =
delete pkt;
PacketPtr big_pkt = send_state->bigPkt;
delete send_state;
-
+
SplitMainSenderState * main_send_state =
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
assert(main_send_state);
}
}
- _status = Running;
+ _status = BaseSimpleCPU::Running;
- Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
+ Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread],
+ traceData);
// keep an instruction count
if (fault == NoFault)
traceData = NULL;
}
- // the locked flag may be cleared on the response packet, so check
- // pkt->req and not pkt to see if it was a load-locked
- if (pkt->isRead() && pkt->req->isLLSC()) {
- TheISA::handleLockedRead(thread, pkt->req);
- }
-
delete pkt->req;
delete pkt;
postExecute();
- if (getState() == SimObject::Draining) {
- advancePC(fault);
- completeDrain();
-
- return;
- }
-
advanceInst(fault);
}
-
void
-TimingSimpleCPU::completeDrain()
+TimingSimpleCPU::updateCycleCounts()
{
- DPRINTF(Config, "Done draining\n");
- changeState(SimObject::Drained);
- drainEvent->process();
+ const Cycles delta(curCycle() - previousCycle);
+
+ numCycles += delta;
+ ppCycles->notify(delta);
+
+ previousCycle = curCycle();
}
void
-TimingSimpleCPU::DcachePort::setPeer(Port *port)
+TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
{
- Port::setPeer(port);
+ for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
+ if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
+ cpu->wakeup(tid);
+ }
+ }
+
+ // Making it uniform across all CPUs:
+ // The CPUs need to be woken up only on an invalidation packet (when using caches)
+ // or on an incoming write packet (when not using caches)
+ // It is not necessary to wake up the processor on all incoming packets
+ if (pkt->isInvalidate() || pkt->isWrite()) {
+ for (auto &t_info : cpu->threadInfo) {
+ TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
+ }
+ }
+}
-#if FULL_SYSTEM
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- cpu->tcBase()->connectMemPorts(cpu->tcBase());
-#endif
+void
+TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
+{
+ for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
+ if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
+ cpu->wakeup(tid);
+ }
+ }
}
bool
-TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
+TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
{
- if (pkt->isResponse() && !pkt->wasNacked()) {
- // delay processing of returned data until next CPU clock edge
- Tick next_tick = cpu->nextCycle(curTick);
-
- if (next_tick == curTick) {
- cpu->completeDataAccess(pkt);
- } else {
- tickEvent.schedule(pkt, next_tick);
- }
+ DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr());
+ // The timing CPU is not really ticked, instead it relies on the
+ // memory system (fetch and load/store) to set the pace.
+ if (!tickEvent.scheduled()) {
+ // Delay processing of returned data until next CPU clock edge
+ tickEvent.schedule(pkt, cpu->clockEdge());
return true;
+ } else {
+ // In the case of a split transaction and a cache that is
+ // faster than a CPU we could get two responses in the
+ // same tick, delay the second one
+ if (!retryRespEvent.scheduled())
+ cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1)));
+ return false;
}
- else if (pkt->wasNacked()) {
- assert(cpu->_status == DcacheWaitResponse);
- pkt->reinitNacked();
- if (!sendTiming(pkt)) {
- cpu->_status = DcacheRetry;
- cpu->dcache_pkt = pkt;
- }
- }
- //Snooping a Coherence Request, do nothing
- return true;
}
void
}
void
-TimingSimpleCPU::DcachePort::recvRetry()
+TimingSimpleCPU::DcachePort::recvReqRetry()
{
// we shouldn't get a retry unless we have a packet that we're
// waiting to transmit
dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
assert(send_state);
PacketPtr big_pkt = send_state->bigPkt;
-
+
SplitMainSenderState * main_send_state =
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
assert(main_send_state);
- if (sendTiming(tmp)) {
+ if (sendTimingReq(tmp)) {
// If we were able to send without retrying, record that fact
// and try sending the other fragment.
send_state->clearFromParent();
cpu->dcache_pkt = NULL;
}
}
- } else if (sendTiming(tmp)) {
+ } else if (sendTimingReq(tmp)) {
cpu->_status = DcacheWaitResponse;
// memory system takes ownership of packet
cpu->dcache_pkt = NULL;
TimingSimpleCPU *
TimingSimpleCPUParams::create()
{
- numThreads = 1;
-#if !FULL_SYSTEM
- if (workload.size() != 1)
- panic("only one workload allowed");
-#endif
return new TimingSimpleCPU(this);
}