Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done...

[gem5.git] / src / cpu / simple / timing.hh

diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 0a3f91e6c5b2069e1dc04ef9154b70c23d9869c6..e405f6a4133b8bd064e256dfb5f4428e6020d0ba 100644 (file)
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -33,102 +33,123 @@
 
 #include "cpu/simple/base.hh"
 
+#include "params/TimingSimpleCPU.hh"
+
 class TimingSimpleCPU : public BaseSimpleCPU
 {
   public:
 
-    struct Params : public BaseSimpleCPU::Params {
-    };
-
-    TimingSimpleCPU(Params *params);
+    TimingSimpleCPU(TimingSimpleCPUParams * params);
     virtual ~TimingSimpleCPU();
 
     virtual void init();
 
   public:
-    //
-    enum Status {
-        Idle,
-        Running,
-        IcacheRetry,
-        IcacheWaitResponse,
-        IcacheWaitSwitch,
-        DcacheRetry,
-        DcacheWaitResponse,
-        DcacheWaitSwitch,
-        SwitchedOut
-    };
-
-  protected:
-    Status _status;
-
-    Status status() const { return _status; }
-
     Event *drainEvent;
 
-    Event *fetchEvent;
-
   private:
 
     class CpuPort : public Port
     {
       protected:
         TimingSimpleCPU *cpu;
+        Tick lat;
 
       public:
 
-        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
-            : Port(_name), cpu(_cpu)
+        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
+            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
         { }
 
+        bool snoopRangeSent;
+
       protected:
 
-        virtual Tick recvAtomic(Packet *pkt);
+        virtual Tick recvAtomic(PacketPtr pkt);
 
-        virtual void recvFunctional(Packet *pkt);
+        virtual void recvFunctional(PacketPtr pkt);
 
         virtual void recvStatusChange(Status status);
 
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
-            AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
+                                            bool &snoop)
+        { resp.clear(); snoop = false; }
+
+        struct TickEvent : public Event
+        {
+            PacketPtr pkt;
+            TimingSimpleCPU *cpu;
+
+            TickEvent(TimingSimpleCPU *_cpu)
+                :Event(&mainEventQueue), cpu(_cpu) {}
+            const char *description() const { return "Timing CPU tick"; }
+            void schedule(PacketPtr _pkt, Tick t);
+        };
+
     };
 
     class IcachePort : public CpuPort
     {
       public:
 
-        IcachePort(TimingSimpleCPU *_cpu)
-            : CpuPort(_cpu->name() + "-iport", _cpu)
+        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
+            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
         { }
 
       protected:
 
-        virtual bool recvTiming(Packet *pkt);
+        virtual bool recvTiming(PacketPtr pkt);
 
         virtual void recvRetry();
+
+        struct ITickEvent : public TickEvent
+        {
+
+            ITickEvent(TimingSimpleCPU *_cpu)
+                : TickEvent(_cpu) {}
+            void process();
+            const char *description() const { return "Timing CPU icache tick"; }
+        };
+
+        ITickEvent tickEvent;
+
     };
 
     class DcachePort : public CpuPort
     {
       public:
 
-        DcachePort(TimingSimpleCPU *_cpu)
-            : CpuPort(_cpu->name() + "-dport", _cpu)
+        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
+            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
         { }
 
+        virtual void setPeer(Port *port);
+
       protected:
 
-        virtual bool recvTiming(Packet *pkt);
+        virtual bool recvTiming(PacketPtr pkt);
 
         virtual void recvRetry();
+
+        struct DTickEvent : public TickEvent
+        {
+            DTickEvent(TimingSimpleCPU *_cpu)
+                : TickEvent(_cpu) {}
+            void process();
+            const char *description() const { return "Timing CPU dcache tick"; }
+        };
+
+        DTickEvent tickEvent;
+
     };
 
     IcachePort icachePort;
     DcachePort dcachePort;
 
-    Packet *ifetch_pkt;
-    Packet *dcache_pkt;
+    PacketPtr ifetch_pkt;
+    PacketPtr dcache_pkt;
+
+    Tick previousTick;
 
   public:
 
@@ -137,9 +158,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-    virtual bool drain(Event *drain_event);
+    virtual unsigned int drain(Event *drain_event);
     virtual void resume();
-    virtual void setMemoryMode(State new_mode);
 
     void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);
@@ -150,14 +170,39 @@ class TimingSimpleCPU : public BaseSimpleCPU
     template <class T>
     Fault read(Addr addr, T &data, unsigned flags);
 
+    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
+            int size, unsigned flags);
+
     template <class T>
     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 
+    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
+            int size, unsigned flags);
+
     void fetch();
-    void completeIfetch(Packet *);
-    void completeDataAccess(Packet *);
+    void completeIfetch(PacketPtr );
+    void completeDataAccess(PacketPtr );
     void advanceInst(Fault fault);
+
+    /**
+     * Print state of address in memory system via PrintReq (for
+     * debugging).
+     */
+    void printAddr(Addr a);
+
   private:
+
+    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
+    FetchEvent *fetchEvent;
+
+    struct IprEvent : Event {
+        Packet *pkt;
+        TimingSimpleCPU *cpu;
+        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
+        virtual void process();
+        virtual const char *description() const;
+    };
+
     void completeDrain();
 };