#include "cpu/simple/base.hh"
+#include "params/TimingSimpleCPU.hh"
+
class TimingSimpleCPU : public BaseSimpleCPU
{
public:
- struct Params : public BaseSimpleCPU::Params {
- };
-
- TimingSimpleCPU(Params *params);
+ TimingSimpleCPU(TimingSimpleCPUParams * params);
virtual ~TimingSimpleCPU();
virtual void init();
public:
- //
- enum Status {
- Idle,
- Running,
- IcacheRetry,
- IcacheWaitResponse,
- IcacheWaitSwitch,
- DcacheRetry,
- DcacheWaitResponse,
- DcacheWaitSwitch,
- SwitchedOut
- };
-
- protected:
- Status _status;
-
- Status status() const { return _status; }
-
Event *drainEvent;
- Event *fetchEvent;
-
private:
class CpuPort : public Port
public:
CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
- : Port(_name), cpu(_cpu), lat(_lat)
+ : Port(_name, _cpu), cpu(_cpu), lat(_lat)
{ }
+ bool snoopRangeSent;
+
protected:
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvStatusChange(Status status);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ bool &snoop)
+ { resp.clear(); snoop = false; }
struct TickEvent : public Event
{
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() const { return "Timing CPU tick"; }
void schedule(PacketPtr _pkt, Tick t);
};
ITickEvent(TimingSimpleCPU *_cpu)
: TickEvent(_cpu) {}
void process();
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() const { return "Timing CPU icache tick"; }
};
ITickEvent tickEvent;
: CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
{ }
+ virtual void setPeer(Port *port);
+
protected:
virtual bool recvTiming(PacketPtr pkt);
DTickEvent(TimingSimpleCPU *_cpu)
: TickEvent(_cpu) {}
void process();
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() const { return "Timing CPU dcache tick"; }
};
DTickEvent tickEvent;
PacketPtr ifetch_pkt;
PacketPtr dcache_pkt;
- int cpu_id;
Tick previousTick;
public:
template <class T>
Fault read(Addr addr, T &data, unsigned flags);
+ Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
+ int size, unsigned flags);
+
template <class T>
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+ Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
+ int size, unsigned flags);
+
void fetch();
void completeIfetch(PacketPtr );
void completeDataAccess(PacketPtr );
void advanceInst(Fault fault);
+
+ /**
+ * Print state of address in memory system via PrintReq (for
+ * debugging).
+ */
+ void printAddr(Addr a);
+
private:
+
+ typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
+ FetchEvent *fetchEvent;
+
+ struct IprEvent : Event {
+ Packet *pkt;
+ TimingSimpleCPU *cpu;
+ IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
+ virtual void process();
+ virtual const char *description() const;
+ };
+
void completeDrain();
};