cpu: o3: replace issueLatency with bool pipelined

[gem5.git] / src / cpu / simple_thread.cc

diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 7876802244b7b29287ca6a5a21fb7ea31bc91390..36603a1c167cd10f908e8ef1578d916d1384f5d8 100644 (file)
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -50,6 +50,7 @@
 #include "mem/fs_translating_port_proxy.hh"
 #include "mem/se_translating_port_proxy.hh"
 #include "params/BaseCPU.hh"
+#include "sim/faults.hh"
 #include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/serialize.hh"
@@ -62,7 +63,8 @@ using namespace std;
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            Process *_process, TheISA::TLB *_itb,
                            TheISA::TLB *_dtb, TheISA::ISA *_isa)
-    : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
+    : ThreadState(_cpu, _thread_num, _process), isa(_isa),
+      predicate(false), system(_sys),
       itb(_itb), dtb(_dtb)
 {
     clearArchRegs();
@@ -107,49 +109,12 @@ SimpleThread::~SimpleThread()
 void
 SimpleThread::takeOverFrom(ThreadContext *oldContext)
 {
-    // some things should already be set up
-    if (FullSystem)
-        assert(system == oldContext->getSystemPtr());
-    assert(process == oldContext->getProcessPtr());
-
-    copyState(oldContext);
-    if (FullSystem) {
-        EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
-        if (quiesce) {
-            // Point the quiesce event's TC at this TC so that it wakes up
-            // the proper CPU.
-            quiesce->tc = tc;
-        }
-        if (quiesceEvent) {
-            quiesceEvent->tc = tc;
-        }
-
-        TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
-        if (stats) {
-            kernelStats = stats;
-        }
-    }
+    ::takeOverFrom(*tc, *oldContext);
+    decoder.takeOverFrom(oldContext->getDecoderPtr());
 
+    kernelStats = oldContext->getKernelStats();
+    funcExeInst = oldContext->readFuncExeInst();
     storeCondFailures = 0;
-
-    oldContext->setStatus(ThreadContext::Halted);
-}
-
-void
-SimpleThread::copyTC(ThreadContext *context)
-{
-    copyState(context);
-
-    if (FullSystem) {
-        EndQuiesceEvent *quiesce = context->getQuiesceEvent();
-        if (quiesce) {
-            quiesceEvent = quiesce;
-        }
-        TheISA::Kernel::Statistics *stats = context->getKernelStats();
-        if (stats) {
-            kernelStats = stats;
-        }
-    }
 }
 
 void
@@ -180,6 +145,12 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     ::unserialize(*tc, cp, section);
 }
 
+void
+SimpleThread::startup()
+{
+    isa->startup(tc);
+}
+
 void
 SimpleThread::dumpFuncProfile()
 {
@@ -189,22 +160,14 @@ SimpleThread::dumpFuncProfile()
 }
 
 void
-SimpleThread::activate(Cycles delay)
+SimpleThread::activate()
 {
     if (status() == ThreadContext::Active)
         return;
 
     lastActivate = curTick();
-
-//    if (status() == ThreadContext::Unallocated) {
-//      cpu->activateWhenReady(_threadId);
-//      return;
-//   }
-
     _status = ThreadContext::Active;
-
-    // status() == Suspended
-    baseCpu->activateContext(_threadId, delay);
+    baseCpu->activateContext(_threadId);
 }
 
 void
@@ -244,3 +207,18 @@ SimpleThread::copyArchRegs(ThreadContext *src_tc)
     TheISA::copyRegs(src_tc, tc);
 }
 
+// The following methods are defined in src/arch/alpha/ev5.cc for
+// Alpha.
+#if THE_ISA != ALPHA_ISA
+Fault
+SimpleThread::hwrei()
+{
+    return NoFault;
+}
+
+bool
+SimpleThread::simPalCheck(int palFunc)
+{
+    return true;
+}
+#endif