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[gem5.git] / src / cpu / simple_thread.hh

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 95848ee2ce2b129175148788199fc9387e7e0f3b..2b79c97081c5b2d1d5c6f6234a2373eae51cf087 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -35,6 +35,7 @@
 #include "arch/isa_traits.hh"
 #include "arch/regfile.hh"
 #include "arch/syscallreturn.hh"
+#include "arch/tlb.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
@@ -49,7 +50,6 @@ class BaseCPU;
 #if FULL_SYSTEM
 
 #include "sim/system.hh"
-#include "arch/tlb.hh"
 
 class FunctionProfile;
 class ProfileNode;
@@ -109,10 +109,8 @@ class SimpleThread : public ThreadState
 
     System *system;
 
-#if FULL_SYSTEM
     TheISA::ITB *itb;
     TheISA::DTB *dtb;
-#endif
 
     // constructor: initialize SimpleThread from given process structure
 #if FULL_SYSTEM
@@ -120,7 +118,8 @@ class SimpleThread : public ThreadState
                  TheISA::ITB *_itb, TheISA::DTB *_dtb,
                  bool use_kernel_stats = true);
 #else
-    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
+    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
+                 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
 #endif
 
     SimpleThread();
@@ -149,10 +148,6 @@ class SimpleThread : public ThreadState
      */
     ThreadContext *getTC() { return tc; }
 
-#if FULL_SYSTEM
-    int getInstAsid() { return regs.instAsid(); }
-    int getDataAsid() { return regs.dataAsid(); }
-
     Fault translateInstReq(RequestPtr &req)
     {
         return itb->translate(req, tc);
@@ -168,27 +163,16 @@ class SimpleThread : public ThreadState
         return dtb->translate(req, tc, true);
     }
 
+#if FULL_SYSTEM
+    int getInstAsid() { return regs.instAsid(); }
+    int getDataAsid() { return regs.dataAsid(); }
+
     void dumpFuncProfile();
 
     Fault hwrei();
 
     bool simPalCheck(int palFunc);
-#else
-
-    Fault translateInstReq(RequestPtr &req)
-    {
-        return process->pTable->translate(req);
-    }
-
-    Fault translateDataReadReq(RequestPtr &req)
-    {
-        return process->pTable->translate(req);
-    }
 
-    Fault translateDataWriteReq(RequestPtr &req)
-    {
-        return process->pTable->translate(req);
-    }
 #endif
 
     /*******************************************
@@ -199,13 +183,13 @@ class SimpleThread : public ThreadState
 
     int getThreadNum() { return tid; }
 
-#if FULL_SYSTEM
-    System *getSystemPtr() { return system; }
-
     TheISA::ITB *getITBPtr() { return itb; }
 
     TheISA::DTB *getDTBPtr() { return dtb; }
 
+#if FULL_SYSTEM
+    System *getSystemPtr() { return system; }
+
     FunctionalPort *getPhysPort() { return physPort; }
 
     /** Return a virtual port. If no thread context is specified then a static
@@ -251,52 +235,62 @@ class SimpleThread : public ThreadState
     //
     uint64_t readIntReg(int reg_idx)
     {
-        return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
+        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+        return regs.readIntReg(flatIndex);
     }
 
     FloatReg readFloatReg(int reg_idx, int width)
     {
-        return regs.readFloatReg(reg_idx, width);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        return regs.readFloatReg(flatIndex, width);
     }
 
     FloatReg readFloatReg(int reg_idx)
     {
-        return regs.readFloatReg(reg_idx);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        return regs.readFloatReg(flatIndex);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx, int width)
     {
-        return regs.readFloatRegBits(reg_idx, width);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        return regs.readFloatRegBits(flatIndex, width);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx)
     {
-        return regs.readFloatRegBits(reg_idx);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        return regs.readFloatRegBits(flatIndex);
     }
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
+        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+        regs.setIntReg(flatIndex, val);
     }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
     {
-        regs.setFloatReg(reg_idx, val, width);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        regs.setFloatReg(flatIndex, val, width);
     }
 
     void setFloatReg(int reg_idx, FloatReg val)
     {
-        regs.setFloatReg(reg_idx, val);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        regs.setFloatReg(flatIndex, val);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
     {
-        regs.setFloatRegBits(reg_idx, val, width);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        regs.setFloatRegBits(flatIndex, val, width);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
-        regs.setFloatRegBits(reg_idx, val);
+        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        regs.setFloatRegBits(flatIndex, val);
     }
 
     uint64_t readPC()
@@ -349,22 +343,22 @@ class SimpleThread : public ThreadState
         regs.setNextNPC(val);
     }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
     {
         return regs.readMiscRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
     {
         return regs.readMiscReg(misc_reg, tc);
     }
 
-    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
     {
         return regs.setMiscRegNoEffect(misc_reg, val);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
     {
         return regs.setMiscReg(misc_reg, val, tc);
     }
@@ -377,15 +371,17 @@ class SimpleThread : public ThreadState
 #if !FULL_SYSTEM
     TheISA::IntReg getSyscallArg(int i)
     {
+        assert(i < TheISA::NumArgumentRegs);
         return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
-                    TheISA::ArgumentReg0 + i));
+                    TheISA::ArgumentReg[i]));
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, TheISA::IntReg val)
     {
+        assert(i < TheISA::NumArgumentRegs);
         regs.setIntReg(TheISA::flattenIntIndex(getTC(),
-                    TheISA::ArgumentReg0 + i), val);
+                    TheISA::ArgumentReg[i]), val);
     }
 
     void setSyscallReturn(SyscallReturn return_value)