SCons: centralize the Dir() workaround for newer versions of scons.

[gem5.git] / src / cpu / simple_thread.hh

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 377bfcd796e60663724bffdebc99154639e39946..4831b701a3e1cba12851c5aa50b71ceac0a01b91 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -197,8 +197,6 @@ class SimpleThread : public ThreadState
 
     BaseCPU *getCpuPtr() { return cpu; }
 
-    int getThreadNum() { return tid; }
-
     TheISA::ITB *getITBPtr() { return itb; }
 
     TheISA::DTB *getDTBPtr() { return dtb; }
@@ -387,8 +385,15 @@ class SimpleThread : public ThreadState
     TheISA::IntReg getSyscallArg(int i)
     {
         assert(i < TheISA::NumArgumentRegs);
-        return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
-                    TheISA::ArgumentReg[i]));
+        TheISA::IntReg val = regs.readIntReg(
+                TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i]));
+#if THE_ISA == SPARC_ISA
+        if (bits(this->readMiscRegNoEffect(
+                        SparcISA::MISCREG_PSTATE), 3, 3)) {
+            val = bits(val, 31, 0);
+        }
+#endif
+        return val;
     }
 
     // used to shift args for indirect syscall
@@ -409,12 +414,6 @@ class SimpleThread : public ThreadState
         process->syscall(callnum, tc);
     }
 #endif
-
-    void changeRegFileContext(TheISA::RegContextParam param,
-            TheISA::RegContextVal val)
-    {
-        regs.changeContext(param, val);
-    }
 };