#include "arch/isa_traits.hh"
#include "arch/regfile.hh"
#include "arch/syscallreturn.hh"
+#include "arch/tlb.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
-#include "mem/physical.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
#if FULL_SYSTEM
#include "sim/system.hh"
-#include "arch/tlb.hh"
class FunctionProfile;
class ProfileNode;
typedef ThreadContext::Status Status;
protected:
- RegFile regs; // correct-path register context
+ RegFile regs; // correct-path register context
public:
// pointer to CPU associated with this SimpleThread
System *system;
-#if FULL_SYSTEM
TheISA::ITB *itb;
TheISA::DTB *dtb;
-#endif
// constructor: initialize SimpleThread from given process structure
#if FULL_SYSTEM
TheISA::ITB *_itb, TheISA::DTB *_dtb,
bool use_kernel_stats = true);
#else
- SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
+ SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
+ TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
#endif
SimpleThread();
*/
ThreadContext *getTC() { return tc; }
-#if FULL_SYSTEM
- int getInstAsid() { return regs.instAsid(); }
- int getDataAsid() { return regs.dataAsid(); }
-
Fault translateInstReq(RequestPtr &req)
{
return itb->translate(req, tc);
return dtb->translate(req, tc, true);
}
- void dumpFuncProfile();
-
- Fault hwrei();
-
- bool simPalCheck(int palFunc);
-#else
-
- Fault translateInstReq(RequestPtr &req)
+ void demapPage(Addr vaddr, uint64_t asn)
{
- return process->pTable->translate(req);
+ itb->demapPage(vaddr, asn);
+ dtb->demapPage(vaddr, asn);
}
- Fault translateDataReadReq(RequestPtr &req)
+ void demapInstPage(Addr vaddr, uint64_t asn)
{
- return process->pTable->translate(req);
+ itb->demapPage(vaddr, asn);
}
- Fault translateDataWriteReq(RequestPtr &req)
+ void demapDataPage(Addr vaddr, uint64_t asn)
{
- return process->pTable->translate(req);
+ dtb->demapPage(vaddr, asn);
}
+
+#if FULL_SYSTEM
+ int getInstAsid() { return regs.instAsid(); }
+ int getDataAsid() { return regs.dataAsid(); }
+
+ void dumpFuncProfile();
+
+ Fault hwrei();
+
+ bool simPalCheck(int palFunc);
+
#endif
/*******************************************
BaseCPU *getCpuPtr() { return cpu; }
- int getThreadNum() { return tid; }
-
-#if FULL_SYSTEM
- System *getSystemPtr() { return system; }
-
TheISA::ITB *getITBPtr() { return itb; }
TheISA::DTB *getDTBPtr() { return dtb; }
- FunctionalPort *getPhysPort() { return physPort; }
+#if FULL_SYSTEM
+ System *getSystemPtr() { return system; }
- /** Return a virtual port. If no thread context is specified then a static
- * port is returned. Otherwise a port is created and returned. It must be
- * deleted by deleteVirtPort(). */
- VirtualPort *getVirtPort(ThreadContext *tc);
+ FunctionalPort *getPhysPort() { return physPort; }
- void delVirtPort(VirtualPort *vp);
+ /** Return a virtual port. This port cannot be cached locally in an object.
+ * After a CPU switch it may point to the wrong memory object which could
+ * mean stale data.
+ */
+ VirtualPort *getVirtPort() { return virtPort; }
#endif
Status status() const { return _status; }
//
uint64_t readIntReg(int reg_idx)
{
- return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
+ int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+ return regs.readIntReg(flatIndex);
}
FloatReg readFloatReg(int reg_idx, int width)
{
- return regs.readFloatReg(reg_idx, width);
+ int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ return regs.readFloatReg(flatIndex, width);
}
FloatReg readFloatReg(int reg_idx)
{
- return regs.readFloatReg(reg_idx);
+ int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ return regs.readFloatReg(flatIndex);
}
FloatRegBits readFloatRegBits(int reg_idx, int width)
{
- return regs.readFloatRegBits(reg_idx, width);
+ int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ return regs.readFloatRegBits(flatIndex, width);
}
FloatRegBits readFloatRegBits(int reg_idx)
{
- return regs.readFloatRegBits(reg_idx);
+ int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ return regs.readFloatRegBits(flatIndex);
}
void setIntReg(int reg_idx, uint64_t val)
{
- regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
+ int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+ regs.setIntReg(flatIndex, val);
}
void setFloatReg(int reg_idx, FloatReg val, int width)
{
- regs.setFloatReg(reg_idx, val, width);
+ int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ regs.setFloatReg(flatIndex, val, width);
}
void setFloatReg(int reg_idx, FloatReg val)
{
- regs.setFloatReg(reg_idx, val);
+ int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ regs.setFloatReg(flatIndex, val);
}
void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
- regs.setFloatRegBits(reg_idx, val, width);
+ int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ regs.setFloatRegBits(flatIndex, val, width);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
- regs.setFloatRegBits(reg_idx, val);
+ int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ regs.setFloatRegBits(flatIndex, val);
}
uint64_t readPC()
regs.setNextNPC(val);
}
- MiscReg readMiscReg(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
{
- return regs.readMiscReg(misc_reg);
+ return regs.readMiscRegNoEffect(misc_reg);
}
- MiscReg readMiscRegWithEffect(int misc_reg)
+ MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
{
- return regs.readMiscRegWithEffect(misc_reg, tc);
+ return regs.readMiscReg(misc_reg, tc);
}
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
- return regs.setMiscReg(misc_reg, val);
+ return regs.setMiscRegNoEffect(misc_reg, val);
}
- void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
- return regs.setMiscRegWithEffect(misc_reg, val, tc);
+ return regs.setMiscReg(misc_reg, val, tc);
}
unsigned readStCondFailures() { return storeCondFailures; }
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{
- return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg0 + i));
+ assert(i < TheISA::NumArgumentRegs);
+ TheISA::IntReg val = regs.readIntReg(
+ TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i]));
+#if THE_ISA == SPARC_ISA
+ if (bits(this->readMiscRegNoEffect(
+ SparcISA::MISCREG_PSTATE), 3, 3)) {
+ val = bits(val, 31, 0);
+ }
+#endif
+ return val;
}
// used to shift args for indirect syscall
void setSyscallArg(int i, TheISA::IntReg val)
{
+ assert(i < TheISA::NumArgumentRegs);
regs.setIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg0 + i), val);
+ TheISA::ArgumentReg[i]), val);
}
void setSyscallReturn(SyscallReturn return_value)
process->syscall(callnum, tc);
}
#endif
-
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
- regs.changeContext(param, val);
- }
};