Merge with head.

[gem5.git] / src / cpu / simple_thread.hh

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 10bbe292c9167b8bc1e2a10e9e589c4dab2a4e02..6c6d5f8429360d731eced568654f52a2f9d6a433 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -33,10 +33,11 @@
 #define __CPU_SIMPLE_THREAD_HH__
 
 #include "arch/isa_traits.hh"
+#include "arch/regfile.hh"
+#include "arch/syscallreturn.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
-#include "mem/physical.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
 #include "sim/eventq.hh"
@@ -250,7 +251,7 @@ class SimpleThread : public ThreadState
     //
     uint64_t readIntReg(int reg_idx)
     {
-        return regs.readIntReg(reg_idx);
+        return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
     }
 
     FloatReg readFloatReg(int reg_idx, int width)
@@ -275,7 +276,7 @@ class SimpleThread : public ThreadState
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        regs.setIntReg(reg_idx, val);
+        regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
     }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
@@ -348,24 +349,24 @@ class SimpleThread : public ThreadState
         regs.setNextNPC(val);
     }
 
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
     {
-        return regs.readMiscReg(misc_reg);
+        return regs.readMiscRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
     {
-        return regs.readMiscRegWithEffect(misc_reg, tc);
+        return regs.readMiscReg(misc_reg, tc);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
     {
-        return regs.setMiscReg(misc_reg, val);
+        return regs.setMiscRegNoEffect(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
     {
-        return regs.setMiscRegWithEffect(misc_reg, val, tc);
+        return regs.setMiscReg(misc_reg, val, tc);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
@@ -376,18 +377,22 @@ class SimpleThread : public ThreadState
 #if !FULL_SYSTEM
     TheISA::IntReg getSyscallArg(int i)
     {
-        return regs.readIntReg(TheISA::ArgumentReg0 + i);
+        assert(i < TheISA::NumArgumentRegs);
+        return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
+                    TheISA::ArgumentReg[i]));
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, TheISA::IntReg val)
     {
-        regs.setIntReg(TheISA::ArgumentReg0 + i, val);
+        assert(i < TheISA::NumArgumentRegs);
+        regs.setIntReg(TheISA::flattenIntIndex(getTC(),
+                    TheISA::ArgumentReg[i]), val);
     }
 
     void setSyscallReturn(SyscallReturn return_value)
     {
-        TheISA::setSyscallReturn(return_value, &regs);
+        TheISA::setSyscallReturn(return_value, getTC());
     }
 
     void syscall(int64_t callnum)