#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
-#include "mem/physical.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
regs.setNextNPC(val);
}
- MiscReg readMiscReg(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
{
- return regs.readMiscReg(misc_reg);
+ return regs.readMiscRegNoEffect(misc_reg);
}
- MiscReg readMiscRegWithEffect(int misc_reg)
+ MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
{
- return regs.readMiscRegWithEffect(misc_reg, tc);
+ return regs.readMiscReg(misc_reg, tc);
}
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
- return regs.setMiscReg(misc_reg, val);
+ return regs.setMiscRegNoEffect(misc_reg, val);
}
- void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
- return regs.setMiscRegWithEffect(misc_reg, val, tc);
+ return regs.setMiscReg(misc_reg, val, tc);
}
unsigned readStCondFailures() { return storeCondFailures; }
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{
+ assert(i < TheISA::NumArgumentRegs);
return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg0 + i));
+ TheISA::ArgumentReg[i]));
}
// used to shift args for indirect syscall
void setSyscallArg(int i, TheISA::IntReg val)
{
+ assert(i < TheISA::NumArgumentRegs);
regs.setIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg0 + i), val);
+ TheISA::ArgumentReg[i]), val);
}
void setSyscallReturn(SyscallReturn return_value)