*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

[gem5.git] / src / cpu / simple_thread.hh

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index f2f79c070b3a424998b1aec26d1059c535bcdb27..824914ad0c2e6e4c2b01c667c684e25a6c629291 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -350,24 +350,24 @@ class SimpleThread : public ThreadState
         regs.setNextNPC(val);
     }
 
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return regs.readMiscReg(misc_reg);
+        return regs.readMiscRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg)
     {
-        return regs.readMiscRegWithEffect(misc_reg, tc);
+        return regs.readMiscReg(misc_reg, tc);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscReg(misc_reg, val);
+        return regs.setMiscRegNoEffect(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscRegWithEffect(misc_reg, val, tc);
+        return regs.setMiscReg(misc_reg, val, tc);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }