/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
#ifndef __CPU_SIMPLE_THREAD_HH__
#define __CPU_SIMPLE_THREAD_HH__
+#include "arch/decoder.hh"
#include "arch/isa.hh"
#include "arch/isa_traits.hh"
#include "arch/registers.hh"
#include "arch/tlb.hh"
#include "arch/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
-#include "cpu/decode.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "debug/FloatRegs.hh"
#include "sim/system.hh"
class BaseCPU;
-
+class CheckerCPU;
class FunctionProfile;
class ProfileNode;
-class FunctionalPort;
-class PhysicalPort;
-class TranslatingPort;
namespace TheISA {
namespace Kernel {
class Statistics;
- };
-};
+ }
+}
/**
* The SimpleThread object provides a combination of the ThreadState
public:
std::string name() const
{
- return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId());
+ return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
}
- // pointer to CPU associated with this SimpleThread
- BaseCPU *cpu;
-
ProxyThreadContext<SimpleThread> *tc;
System *system;
TheISA::TLB *itb;
TheISA::TLB *dtb;
- Decoder decoder;
+ TheISA::Decoder decoder;
// constructor: initialize SimpleThread from given process structure
// FS
TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats = true);
// SE
- SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
- TheISA::TLB *_itb, TheISA::TLB *_dtb);
+ SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
+ Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
SimpleThread();
* ThreadContext interface functions.
******************************************/
- BaseCPU *getCpuPtr() { return cpu; }
+ BaseCPU *getCpuPtr() { return baseCpu; }
TheISA::TLB *getITBPtr() { return itb; }
TheISA::TLB *getDTBPtr() { return dtb; }
- Decoder *getDecoderPtr() { return &decoder; }
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
- System *getSystemPtr() { return system; }
+ TheISA::Decoder *getDecoderPtr() { return &decoder; }
- FunctionalPort *getPhysPort() { return physPort; }
-
- /** Return a virtual port. This port cannot be cached locally in an object.
- * After a CPU switch it may point to the wrong memory object which could
- * mean stale data.
- */
- VirtualPort *getVirtPort() { return virtPort; }
+ System *getSystemPtr() { return system; }
Status status() const { return _status; }
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
- void activate(int delay = 1);
+ void activate(Cycles delay = Cycles(1));
/// Set the status to Suspended.
void suspend();
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- floatRegs.i[flatIndex] = val;
+ // XXX: Fix array out of bounds compiler error for gem5.fast
+ // when checkercpu enabled
+ if (flatIndex < TheISA::NumFloatRegs)
+ floatRegs.i[flatIndex] = val;
DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
}
_pcState = val;
}
+ void
+ pcStateNoRecord(const TheISA::PCState &val)
+ {
+ _pcState = val;
+ }
+
Addr
instAddr()
{