/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2001-2006 The Regents of The University of Michigan
* All rights reserved.
*
#ifndef __CPU_SIMPLE_THREAD_HH__
#define __CPU_SIMPLE_THREAD_HH__
+#include "arch/decoder.hh"
#include "arch/isa.hh"
#include "arch/isa_traits.hh"
-#include "arch/regfile.hh"
+#include "arch/registers.hh"
#include "arch/tlb.hh"
#include "arch/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
+#include "debug/FloatRegs.hh"
+#include "debug/IntRegs.hh"
+#include "mem/page_table.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
+#include "sim/process.hh"
#include "sim/serialize.hh"
+#include "sim/system.hh"
class BaseCPU;
-
-#if FULL_SYSTEM
-
-#include "sim/system.hh"
+class CheckerCPU;
class FunctionProfile;
class ProfileNode;
-class FunctionalPort;
-class PhysicalPort;
namespace TheISA {
namespace Kernel {
class Statistics;
- };
-};
-
-#else // !FULL_SYSTEM
-
-#include "sim/process.hh"
-#include "mem/page_table.hh"
-class TranslatingPort;
-
-#endif // FULL_SYSTEM
+ }
+}
/**
* The SimpleThread object provides a combination of the ThreadState
class SimpleThread : public ThreadState
{
protected:
- typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef ThreadContext::Status Status;
protected:
- RegFile regs; // correct-path register context
union {
FloatReg f[TheISA::NumFloatRegs];
FloatRegBits i[TheISA::NumFloatRegs];
TheISA::IntReg intRegs[TheISA::NumIntRegs];
TheISA::ISA isa; // one "instance" of the current ISA.
+ TheISA::PCState _pcState;
+
+ /** Did this instruction execute or is it predicated false */
+ bool predicate;
+
public:
- // pointer to CPU associated with this SimpleThread
- BaseCPU *cpu;
+ std::string name() const
+ {
+ return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
+ }
ProxyThreadContext<SimpleThread> *tc;
TheISA::TLB *itb;
TheISA::TLB *dtb;
+ TheISA::Decoder decoder;
+
// constructor: initialize SimpleThread from given process structure
-#if FULL_SYSTEM
+ // FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats = true);
-#else
- SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
- TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
-#endif
+ // SE
+ SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
+ Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
SimpleThread();
dtb->demapPage(vaddr, asn);
}
-#if FULL_SYSTEM
- int getInstAsid() { return isa.instAsid(); }
- int getDataAsid() { return isa.dataAsid(); }
-
void dumpFuncProfile();
Fault hwrei();
bool simPalCheck(int palFunc);
-#endif
-
/*******************************************
* ThreadContext interface functions.
******************************************/
- BaseCPU *getCpuPtr() { return cpu; }
+ BaseCPU *getCpuPtr() { return baseCpu; }
TheISA::TLB *getITBPtr() { return itb; }
TheISA::TLB *getDTBPtr() { return dtb; }
- System *getSystemPtr() { return system; }
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
-#if FULL_SYSTEM
- FunctionalPort *getPhysPort() { return physPort; }
+ TheISA::Decoder *getDecoderPtr() { return &decoder; }
- /** Return a virtual port. This port cannot be cached locally in an object.
- * After a CPU switch it may point to the wrong memory object which could
- * mean stale data.
- */
- VirtualPort *getVirtPort() { return virtPort; }
-#endif
+ System *getSystemPtr() { return system; }
Status status() const { return _status; }
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
- void activate(int delay = 1);
+ void activate(Cycles delay = Cycles(1));
/// Set the status to Suspended.
void suspend();
virtual bool misspeculating();
- Fault instRead(RequestPtr &req)
- {
- panic("instRead not implemented");
- // return funcPhysMem->read(req, inst);
- return NoFault;
- }
-
void copyArchRegs(ThreadContext *tc);
void clearArchRegs()
{
- regs.clear();
+ _pcState = 0;
memset(intRegs, 0, sizeof(intRegs));
memset(floatRegs.i, 0, sizeof(floatRegs.i));
+ isa.clear();
}
//
{
int flatIndex = isa.flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
- return intRegs[flatIndex];
+ uint64_t regVal = intRegs[flatIndex];
+ DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
+ reg_idx, flatIndex, regVal);
+ return regVal;
}
FloatReg readFloatReg(int reg_idx)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- return floatRegs.f[flatIndex];
+ FloatReg regVal = floatRegs.f[flatIndex];
+ DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
+ reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
+ return regVal;
}
FloatRegBits readFloatRegBits(int reg_idx)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- return floatRegs.i[flatIndex];
+ FloatRegBits regVal = floatRegs.i[flatIndex];
+ DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
+ reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
+ return regVal;
}
void setIntReg(int reg_idx, uint64_t val)
{
int flatIndex = isa.flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
+ DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
+ reg_idx, flatIndex, val);
intRegs[flatIndex] = val;
}
int flatIndex = isa.flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
floatRegs.f[flatIndex] = val;
+ DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
+ reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- floatRegs.i[flatIndex] = val;
+ // XXX: Fix array out of bounds compiler error for gem5.fast
+ // when checkercpu enabled
+ if (flatIndex < TheISA::NumFloatRegs)
+ floatRegs.i[flatIndex] = val;
+ DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
+ reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
}
- uint64_t readPC()
+ TheISA::PCState
+ pcState()
{
- return regs.readPC();
+ return _pcState;
}
- void setPC(uint64_t val)
- {
- regs.setPC(val);
- }
-
- uint64_t readMicroPC()
- {
- return microPC;
- }
-
- void setMicroPC(uint64_t val)
+ void
+ pcState(const TheISA::PCState &val)
{
- microPC = val;
+ _pcState = val;
}
- uint64_t readNextPC()
+ void
+ pcStateNoRecord(const TheISA::PCState &val)
{
- return regs.readNextPC();
+ _pcState = val;
}
- void setNextPC(uint64_t val)
+ Addr
+ instAddr()
{
- regs.setNextPC(val);
+ return _pcState.instAddr();
}
- uint64_t readNextMicroPC()
+ Addr
+ nextInstAddr()
{
- return nextMicroPC;
+ return _pcState.nextInstAddr();
}
- void setNextMicroPC(uint64_t val)
+ MicroPC
+ microPC()
{
- nextMicroPC = val;
+ return _pcState.microPC();
}
- uint64_t readNextNPC()
+ bool readPredicate()
{
- return regs.readNextNPC();
+ return predicate;
}
- void setNextNPC(uint64_t val)
+ void setPredicate(bool val)
{
- regs.setNextNPC(val);
+ predicate = val;
}
MiscReg
void setStCondFailures(unsigned sc_failures)
{ storeCondFailures = sc_failures; }
-#if !FULL_SYSTEM
void syscall(int64_t callnum)
{
process->syscall(callnum, tc);
}
-#endif
};
projects / gem5.git / blobdiff