cpu: O3 add a header declaring the DerivO3CPU

[gem5.git] / src / cpu / simple_thread.hh

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 48077a9b92bdf39070ea19bd4cb84bfafeaa5285..8594e44712f02be4dc7e30d2150365a206ff6d96 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2001-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -32,45 +44,37 @@
 #ifndef __CPU_SIMPLE_THREAD_HH__
 #define __CPU_SIMPLE_THREAD_HH__
 
+#include "arch/decoder.hh"
 #include "arch/isa.hh"
 #include "arch/isa_traits.hh"
 #include "arch/registers.hh"
 #include "arch/tlb.hh"
 #include "arch/types.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
+#include "debug/FloatRegs.hh"
+#include "debug/IntRegs.hh"
+#include "mem/page_table.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
 #include "sim/eventq.hh"
+#include "sim/process.hh"
 #include "sim/serialize.hh"
+#include "sim/system.hh"
 
 class BaseCPU;
-
-#if FULL_SYSTEM
-
-#include "sim/system.hh"
+class CheckerCPU;
 
 class FunctionProfile;
 class ProfileNode;
-class FunctionalPort;
-class PhysicalPort;
 
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
-
-#else // !FULL_SYSTEM
-
-#include "sim/process.hh"
-#include "mem/page_table.hh"
-class TranslatingPort;
-
-#endif // FULL_SYSTEM
+    }
+}
 
 /**
  * The SimpleThread object provides a combination of the ThreadState
@@ -112,8 +116,10 @@ class SimpleThread : public ThreadState
     bool predicate;
 
   public:
-    // pointer to CPU associated with this SimpleThread
-    BaseCPU *cpu;
+    std::string name() const
+    {
+        return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
+    }
 
     ProxyThreadContext<SimpleThread> *tc;
 
@@ -122,15 +128,16 @@ class SimpleThread : public ThreadState
     TheISA::TLB *itb;
     TheISA::TLB *dtb;
 
+    TheISA::Decoder decoder;
+
     // constructor: initialize SimpleThread from given process structure
-#if FULL_SYSTEM
+    // FS
     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
                  TheISA::TLB *_itb, TheISA::TLB *_dtb,
                  bool use_kernel_stats = true);
-#else
-    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
-                 TheISA::TLB *_itb, TheISA::TLB *_dtb);
-#endif
+    // SE
+    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
+                 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
 
     SimpleThread();
 
@@ -174,36 +181,27 @@ class SimpleThread : public ThreadState
         dtb->demapPage(vaddr, asn);
     }
 
-#if FULL_SYSTEM
     void dumpFuncProfile();
 
     Fault hwrei();
 
     bool simPalCheck(int palFunc);
 
-#endif
-
     /*******************************************
      * ThreadContext interface functions.
      ******************************************/
 
-    BaseCPU *getCpuPtr() { return cpu; }
+    BaseCPU *getCpuPtr() { return baseCpu; }
 
     TheISA::TLB *getITBPtr() { return itb; }
 
     TheISA::TLB *getDTBPtr() { return dtb; }
 
-    System *getSystemPtr() { return system; }
+    CheckerCPU *getCheckerCpuPtr() { return NULL; }
 
-#if FULL_SYSTEM
-    FunctionalPort *getPhysPort() { return physPort; }
+    TheISA::Decoder *getDecoderPtr() { return &decoder; }
 
-    /** Return a virtual port. This port cannot be cached locally in an object.
-     * After a CPU switch it may point to the wrong memory object which could
-     * mean stale data.
-     */
-    VirtualPort *getVirtPort() { return virtPort; }
-#endif
+    System *getSystemPtr() { return system; }
 
     Status status() const { return _status; }
 
@@ -211,7 +209,7 @@ class SimpleThread : public ThreadState
 
     /// Set the status to Active.  Optional delay indicates number of
     /// cycles to wait before beginning execution.
-    void activate(int delay = 1);
+    void activate(Cycles delay = Cycles(1));
 
     /// Set the status to Suspended.
     void suspend();
@@ -286,7 +284,10 @@ class SimpleThread : public ThreadState
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
-        floatRegs.i[flatIndex] = val;
+        // XXX: Fix array out of bounds compiler error for gem5.fast
+        // when checkercpu enabled
+        if (flatIndex < TheISA::NumFloatRegs)
+            floatRegs.i[flatIndex] = val;
         DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
                 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
     }
@@ -303,6 +304,12 @@ class SimpleThread : public ThreadState
         _pcState = val;
     }
 
+    void
+    pcStateNoRecord(const TheISA::PCState &val)
+    {
+        _pcState = val;
+    }
+
     Addr
     instAddr()
     {
@@ -372,12 +379,10 @@ class SimpleThread : public ThreadState
     void setStCondFailures(unsigned sc_failures)
     { storeCondFailures = sc_failures; }
 
-#if !FULL_SYSTEM
     void syscall(int64_t callnum)
     {
         process->syscall(callnum, tc);
     }
-#endif
 };